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0220-2024-10-11.md | 0222-2024-11-11.md |
TT Discord channel #ttihp0p2-tapeout
discusses an experimental IHP PDK tapeout open for contributions, following the closed tinytapeout-ihp-0p1 tapeout. I was lucky to have TT07's raybox-zero selected for that earlier one.
I used ttihp-verilog-template to try creating a couple of projects...
I replicated my simple solo-squash Pong-like VGA game as submitted to TT03p5: https://github.com/algofoogle/ttihp-solo-squash -- it seems to harden fine via the GHAs.
I need to implement tests and have a mode option to select between "classic", TinyVGA Pmod, and potentially other output modes.
NOTE: This flow uses ORFS instead of OpenLane. Might also be incomplete from a TT standpoint (e.g. no GL sim yet, at least not in GHA?). Here's what I did to set it up:
- Fork https://github.com/TinyTapeout/ttihp-verilog-template => https://github.com/algofoogle/ttihp-solo-squash
- Settings => Pages => Source: GitHub Actions
- Actions => Enable
- Clone to my VM in
~/projects/ttihp-solo-squash
- NOTE: Last time I submitted to TT it was TT03p5 (and it included the lzc test) but since then I've also submitted to GF180. Need to compare code versions: tt03p5 & GF180 are static copies, but there's also solo-squash-caravel-v2 which has it as a submodule.
- For now, I'll add the (currently) latest commit of solo_squash as a submodule...
cd src git submodule add https://github.com/algofoogle/solo_squash
- I'll also add a copy of lzc_fast.v and then use top.v as taken from tt03p5.
- I merged
top.v
intoproject.v
. NOTE: Original top.v uses`timescale
but project.v does not. - DON'T FORGET: Need to make the VGA pinout (and possibly audio) match TT standards (e.g. TinyVGA).
- Update
info.yaml
, mostly transposed from tt03p5 version. - Update README a little.
- Update
docs/info.md
- In
project.v
, make sure unused inputs are referenced to suppress warnings.
test
action failed but gds
and docs
passed.
Utilisation of 1x1 tile is ~32%.
This is in the gds
action:
Extracting clock period from SDC file: /home/runner/work/ttihp-solo-squash/ttihp-solo-squash/runs/wokwi/results/ihp-sg13g2/tt-submission/base/clock_period.txt
Setting clock period to 20000
Is that 20ns? Where does it come from?
This warning is also shown in the GDS summary page, but I assume we can ignore this:
Warning: Found unsupported expression 'SCE*SCD+SCE'*D' in pin attribute of cell 'sg13g2_sdfbbp_1' - skipping.
I tried to put the TT07 version of raybox-zero into the template (note: rbz
branch of that repo). I can get it to harden, but it fails DRC -- evidently a bug (maybe in ORFS) to do with Metal2 area being too small in some cases.
I should file a bug with a reproducible, but not sure how to do that yet.
I was hardening at 6x2. I managed to get the flow to run locally and I got it to just barely harden successfully in 4x2 tiles with a PLACE_DENSITY
of 0.78.
Getting the flow to run locally took a little fiddling, and one thing I recall was doing sudo apt install python3-tk
. Here's the ttihp-env.sh
file I ended up creating in the repo dir:
#!/bin/bash
export FLOW=orfs
export FLOW_ARG=--orfs
export IHP_PDK_ROOT=/home/anton/ttsetup@tt09-ihp/pdk
export IHP_PDK_COMMIT=69c58d9ba56d8894c1499b2dd2689f5e22692704
export ORFS_ROOT=/home/anton/ttsetup@tt09-ihp/orfs
export ORFS_COMMIT=ad1c669e5bfaf57b2b6e9c017c7255182d461190
export OPENROAD_EXE=/usr/bin/openroad
export YOSYS_EXE=/home/anton/ttsetup@tt09-ihp/oss-cad-suite/bin/yosys
source /home/anton/ttsetup@tt09-ihp/venv/bin/activate