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2310C.md

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Tip 2310C: Checks to do on final chipIgnite submission

These are just notes for myself: Checks I need to remember to do to be sure my chipIgnite submission is good to go...

  • Which version of OpenLane should I be using?
  • Look for antenna violations: (VIOLATED)
  • Check setup/hold margins
  • Regular simulation
  • Caravel firmware
  • GL simulation
  • Account for every input, output, and oeb
  • Implement la_oenb check: i.e. if the design senses an la_oenb==1 on something, that implies the design is meant to provide the output back to VexRisc. However, we expect all of them to be inputs into our design, so la_oenb==1 would mean misconfiguration, so our respective inputs would be floating and potentially chaotic... we could instead detect this case and just mux the respective LA to be 0.
    • NOTE: This might not be necessary. From looking at tests where LA lines are set to be inputs (into VexRisc), it appears la_data_in switches to 0 anyway.
  • Pay attention to setting io_oeb[*] for analog pins
  • Make sure my oebs match the polarity of the intended target. Matt prefers 1=output, Caravel has a mix of 0=out and 1=out. Check this (and actual direction) for both LA and IOs.
  • Scour logs/synthesis/1-synthesis.log for warnings/errors
  • Look at GDS in KLayout and make sure every pin is wired up sensibly
  • Check CTS
  • Make sure we're using correct directives in config.tcl
  • Make sure RESET definitely suspends all switching, even if we still have a clock coming in. This is to make sure we don't create noise for other designs on the chip (esp. analog ones).
  • Implement safe reset lock using XOR method via LA.
  • Work out correct clock source. Is it user_clock2? Make sure CLOCK_PORT and CLOCK_NET are set correctly!
  • Check FP_PIN_ORDER_CFG
  • No logic in UPW level!
  • Make sure no IO double-ups (typos)
  • Make sure nothing UNassigned... check for all assignments, ranges, counts, even if otherwise unused.