Digital VLSI Soc-Physical Design (Picorv32)

DAY-1: Inception of open-sourcs EDA,OpenLANE and sky130 PDK

OpenLANE software

OpenLane is a complete toolchain used for physical design in digital VLSI circuits. It is part of the broader open-source hardware initiative and is specifically designed to handle the RTL-to-GDSII flow, automating the steps between Register-Transfer Level (RTL) design and the final layout for chip manufacturing (GDSII). OpenLane is built on top of various other open-source tools to facilitate this process.

Key Features:

1. RTL to GDSII Automation: OpenLane automates the process of taking RTL designs (usually written in VHDL/Verilog) through the physical design flow, up to generating GDSII files that can be sent to a fabrication foundry.

2.Open-Source Tool Integration: OpenLane integrates multiple open-source tools, such as:

• Yosys: For synthesis, translating RTL to a gate-level netlist.
• OpenROAD: For place-and-route, performing physical layout steps.
• Magic: For layout viewing and DRC (Design Rule Checking).
• Netgen: For LVS (Layout vs. Schematic) checking.
• KLayout: For GDSII manipulation and visualization.

3. Flow Steps:

• Synthesis: Translates RTL into a gate-level netlist.
• Floorplanning: Determines how the major blocks will be arranged on the chip.
• Placement: Places standard cells on the floorplan.
• Routing: Routes the wires that connect the standard cells.
• Timing Analysis: Ensures that the design meets timing requirements.
• Power and Ground Network (P/G): Establishes a network for power delivery and grounding.
• Design Rule Checking (DRC): Ensures the design conforms to the fabrication process rules.
• Layout vs. Schematic (LVS) Verification: Confirms that the layout matches the circuit's schematic.

4. Customizable Flow: Users can configure the tool to match different process technology nodes and design constraints.

5. Technology Compatibility: It supports different PDKs (Process Design Kits), including the open-source SkyWater 130nm process.

RISC-V (picorv32a)

The PicoRV32 is a compact and efficient open-source implementation of a 32-bit RISC-V CPU, designed primarily for use in FPGAs (Field Programmable Gate Arrays) and other resource-constrained environments. It is fully compliant with the RISC-V RV32IMC instruction set architecture, which supports 32-bit instructions, integer arithmetic, multiplication/division, and compressed instructions (reduced-length instructions for improved code density).

The core is highly optimized for small area usage and low resource consumption, making it suitable for tasks where minimal power and resources are available.

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Day 1 Lab : Design setup

 cd Desktop/work/tool/openlane_working_dir/openlane
 docker
 ./flow.tcl -interactive

 prep -design picorv32a

 run_synthesis 

Results

 Flop Ratio 

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DAY-2 lab: Floorplaning and Placement

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 cd Desktop/work/tool/openlane_working_dir/openlane/designs/picorv32a
 less config.tcl

Floorplan

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FP_IO_VMETAL

FP_IO_HMETAL

 run_floorplan
 cd Desktop/work/tool/openlane_working_dir/openlane/configuration

 cd Desktop/work/tool/openlane_working_dir/openlane/designs/picorv32a/08-09_14-03/results/floorplan
 magic -T /home/vsduser/Desktop/work/tool/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &

Metal 3 cell

Metal 2 cell

Buffer cell

Nand cell

Decoupling capacitor cell

tapvpwrvgnd cell

Placement

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 run_placement

magic -T /home/vsduser/Desktop/work/tool/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

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DAY-3 lab: Designing Library cell and ngSPICE characterization

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Cloning custom inverter standard cell design from github repository

 git clone https://github.com/nickson-jose/vsdstdcelldesign.git

Copying magic tech file to vsdstdcelldesign

 cp sky130A.tech /home/vsduser/Desktop/work/tool/openlane_working_dir/openplane/vsdstdcelldesign

custom CMOS inverter in magic tool

N-MOS in custom CMOS inverter in magic tool

P-MOS in custom CMOS inverter in magic tool

"A" is attached to locali in cell def sky130_inv

"Y" is attached to locali in cell def sky130_inv

Poly-silicon in custom CMOS inverter in magic tool

Extracting CMOS inverter to SPICE characterization

 pwd
 extract all
 ext2spice cthresh 0 rthresh 0
 ext2spice

Opening SPICE extracted file

 vim sky130_inv.spice

Running and ploting the SPICE file

 ngspice sky130_inv.spice
 plot y vs time a

Rise time calculation

 Rise Time = T(80%)−T(20%)

80% of 3.3V = 2.64

20% of 3.3V = 0.660

 Rise Time = 0.05933ns

Fall time calculation

 Fall Time = T(80%)−T(20%)

80% of 3.3V = 2.64

20% of 3.3V = 0.660

  Fall Time = 0.02999ns

Rise propagation delay calculation

 Rise Delay= Tout(50%)​ − Tin(50%)​

50% of 3.3V = 1.65

 Rise propagation delay = 0.05639ns

Fall propagation delay calculation

 Fall Delay= Tout(50%)​ − Tin(50%)​

50% of 3.3V = 1.65

 Fall propagation delay = 0.0248ns

Introduction to magic tool options and steps to load sky130 DRC rules

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Lab introduction to Magic and steps to load Sky130 tech-rules

 wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz
 tar xfz drc_tests.tgz
 cd drc_tests

To view .magicrc file

 gvim .magicrc

Open magic tool

 magic -d XR &

DRC check exercise

 load poly

poly.9

DRC rule for poly.9 in skywater130A pdk

npolyres

poly

xpolyres

ppolyres

drc check
drc why

vi sky130A.tech

/drc

/poly.9

Error-1

Error-2

Error-2 (fixed)

Error-1 (fixed)

 tech load sky130A.tech
 drc check
 drc why

Poly.2

DRC rule for poly.2 in skywater130A pdk

Error

Error (fixed)

nwell.4

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DAY-4 lab: Pre-layout timing analysis and importance of good clock tree

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Open CMOS -inverter layout using magic tool

 press g on the layout for the grid formate

Generation of LEF file from layout

 Requirment_1.The input and output ports of the standard cell should lie on the intersection of the vertical and horizontal tracks.

 % grid 0.46um 0.34um 0.23um 0.17um

 Requirement_2: Width of the standard cell must be odd multiple of the Xpitch.

 Requriement_3: Hight of the standard cell must be even multiple of the Ypitch

Create port definition

Set port class and port use

Creating LEF file with same custom file name

 % write lef

copying sky130_vsdinv.lef from (openlane/vsdstdcelldesign) to (picorv32a/src)

 cp sky130_vsdinv.lef /home/Desktop/work/tool/openlane_working_dir/openlane/designs/picorv32a/src

copying sky130_fd_sc_hd_*.lib file from (openlane/vsdstdcelldesign/libs) to (picorv32a/src)

cp sky130_fd_sc_hd_* /home/Desktop/work/tool/openlane_working_dir/openlane/designs/picorv32a/src

Editing (config.tcl)

set ::env(LIB_SYNTH) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"
set ::env(LIB_FASTEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__fast.lib"
set ::env(LIB_SLOWEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__slow.lib"
set ::env(LIB_TYPICAL) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"

set ::env(EXTRA_LEFS) [glob $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/src/*.lef]

Plugging custom LEF to openlane flow

 docker
 ./flow.tcl -interactive
 package require openlane 0.9
 prep -design picorv32a -tag 08-09_14-03 -overwrite
 run_synthsis

 total negative slack (tns) = -711.59
 wrost negative slack (wns0 = -23.89

For reducing slack

 set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
 add_lefs -src $lefs
 echo $::env(SYNTH_STRATEGY)
 set ::env(SYNTH_STRATEGY) "DELAY 1"
 echo $::env(SYNTH_BUFFERING)
 echo $::env(SYNTH_SIZING)
 set ::env(SYNTH_SIZING) 1
 echo $::env(SYNTH_DRIVING_CELL)

 total negative slack (tns) = 0.00
 wrost negative slack (wns0 = 0.00

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 run_floorplan
 run_placement

  magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

Expanding sky130_vsdinv custom block

   % expand

Create (pre_sta.conf) for STA analysis in openlane directory

Create (my_base.sdc) for STA analysis in openlane/designs/picorv32a/src

Output of pre_sta.conf is equal to synthesis stage

    sta pre_sta.conf

The slack is (7.14)

The slack should be greater than or equal to 0

   SLACK = (DATA REQUIRED TIME) - (DATA ARIVAL TIME)

Replace the old netlist with the newly generated netlist

 write_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/08-09_14-03/results/synthesis/picorv32a.synthesis.v

 run_floorplan
 run_placement

run_cts

Generated cts file

/home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/08-09_14-03/results/synthesis

Post-CTS timing analysis using OpenROAD

openroad

read_lef /openLANE_flow/designs/picorv32a/runs/08-09_14-03/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/08-09_14-03/results/cts/picorv32a.cts.def
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/08-09_14-03/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4

Post-CTS OpenROAD timing analysis by removing 'sky130_fd_sc_hd__clkbuf_1' cell from clock buffer list variable 'CTS_CLK_BUFFER_LIST'.

exit
echo $::env(CTS_CLK_BUFFER_LIST)
set ::env(CTS_CLK_BUFFER_LIST) [lreplace $::env(CTS_CLK_BUFFER_LIST) 0 0]
echo $::env(CTS_CLK_BUFFER_LIST)

echo $::env(CURRENT_DEF)
set ::env(CURRENT_DEF) /openLANE_flow/designs/picorv32a/runs/08-09_14-03/results/placement/picorv32a.placement.def

run_cts

echo $::env(CTS_CLK_BUFFER_LIST)
openroad
read_lef /openLANE_flow/designs/picorv32a/runs/08-09_14-03/tmp/merged.lef
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/08-09_14-03/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4

report_clock_skew -hold
report_clock_skew -setup

echo $::env(CTS_CLK_BUFFER_LIST)
set ::env(CTS_CLK_BUFFER_LIST) [linsert $::env(CTS_CLK_BUFFER_LIST) 0 sky130_fd_sc_hd__clkbuf_1]
echo $::env(CTS_CLK_BUFFER_LIST)

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DAY-5 lab: Final steps for RTL2GDS using tritonRoute and openSTA

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Power distibution network

docker
./flow.tcl -interactive
package require openlane 0.9
prep -design picorv32a
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
set ::env(SYNTH_STRATEGY) "DELAY 1"
set ::env(SYNTH_SIZING) 1
run_synthesis
init_floorplan
place_io
tap_decap_or
run_placement
run_cts
gen_pdn

Load PDN def in magic

 cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-09_05-11/tmp/floorplan/
 magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read 14-pdn.def &

Routing

echo $::env(CURRENT_DEF)
echo $::env(ROUTING_STRATEGY)
run_routing

0th optimization

57th optimization

Commands to load routed def in magic in another terminal

  cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-09_05-011/results/routing/
  magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.def &

fast route guide

  openlane/designs/picorv32a/runs/17-09_05-11/tmp/routing
  less 15-fastroute.guide

Post-Route parasitic extraction using SPEF extractor

  cd Desktop/work/tools/SPEF_EXTRACTOR
  python3 main.py /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-09_05-11/tmp/merged.lef /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-09_05-11/results/routing/picorv32a.def

Post-Route OpenSTA timing analysis with the extracted parasitics

docker
./flow.tcl -interactive
package require openlane 0.9
prep -design picorv32a -tag 17-09_05-11

openroad
read_lef /openLANE_flow/designs/picorv32a/runs/17-09_05-07/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/17-09_05-07/results/routing/picorv32a.def
write_db pico_route.db
read_db pico_route.db
read_verilog /openLANE_flow/designs/picorv32a/runs/17-09_05-07/results/synthesis/picorv32a.synthesis_preroute.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
read_spef /openLANE_flow/designs/picorv32a/runs/17-09_05-07/results/routing/picorv32a.spef
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4
exit

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Acknowledgements

• Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.
• Nickson P Jose, Physical Design Engineer, Intel Corporation.
• R. Timothy Edwards, Senior Vice President of Analog and Design, efabless Corporation.

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