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Digital VLSI Soc-Physical Design (Picorv32)

DAY-1: Inception of open-sourcs EDA,OpenLANE and sky130 PDK

OpenLANE software

image

OpenLane is a complete toolchain used for physical design in digital VLSI circuits. It is part of the broader open-source hardware initiative and is specifically designed to handle the RTL-to-GDSII flow, automating the steps between Register-Transfer Level (RTL) design and the final layout for chip manufacturing (GDSII). OpenLane is built on top of various other open-source tools to facilitate this process.

Key Features:

1. RTL to GDSII Automation: OpenLane automates the process of taking RTL designs (usually written in VHDL/Verilog) through the physical design flow, up to generating GDSII files that can be sent to a fabrication foundry.

2.Open-Source Tool Integration: OpenLane integrates multiple open-source tools, such as:

  • Yosys: For synthesis, translating RTL to a gate-level netlist.
  • OpenROAD: For place-and-route, performing physical layout steps.
  • Magic: For layout viewing and DRC (Design Rule Checking).
  • Netgen: For LVS (Layout vs. Schematic) checking.
  • KLayout: For GDSII manipulation and visualization.

3. Flow Steps:

  • Synthesis: Translates RTL into a gate-level netlist.
  • Floorplanning: Determines how the major blocks will be arranged on the chip.
  • Placement: Places standard cells on the floorplan.
  • Routing: Routes the wires that connect the standard cells.
  • Timing Analysis: Ensures that the design meets timing requirements.
  • Power and Ground Network (P/G): Establishes a network for power delivery and grounding.
  • Design Rule Checking (DRC): Ensures the design conforms to the fabrication process rules.
  • Layout vs. Schematic (LVS) Verification: Confirms that the layout matches the circuit's schematic.

4. Customizable Flow: Users can configure the tool to match different process technology nodes and design constraints.

5. Technology Compatibility: It supports different PDKs (Process Design Kits), including the open-source SkyWater 130nm process.

RISC-V (picorv32a)

PADS

The PicoRV32 is a compact and efficient open-source implementation of a 32-bit RISC-V CPU, designed primarily for use in FPGAs (Field Programmable Gate Arrays) and other resource-constrained environments. It is fully compliant with the RISC-V RV32IMC instruction set architecture, which supports 32-bit instructions, integer arithmetic, multiplication/division, and compressed instructions (reduced-length instructions for improved code density).

The core is highly optimized for small area usage and low resource consumption, making it suitable for tasks where minimal power and resources are available.

Day 1 Lab : Design setup

 cd Desktop/work/tool/openlane_working_dir/openlane
 docker
 ./flow.tcl -interactive

1

 prep -design picorv32a

2

 run_synthesis

Results

3 4

 Flop Ratio

5

DAY-2 lab: Floorplaning and Placement

 cd Desktop/work/tool/openlane_working_dir/openlane/designs/picorv32a
 less config.tcl

1

Floorplan

FP_IO_VMETAL

FP_IO_HMETAL

 run_floorplan
 cd Desktop/work/tool/openlane_working_dir/openlane/configuration

2

 cd Desktop/work/tool/openlane_working_dir/openlane/designs/picorv32a/08-09_14-03/results/floorplan
 magic -T /home/vsduser/Desktop/work/tool/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &

3

Metal 3 cell

4

5

Metal 2 cell

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Buffer cell

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Nand cell

8

Decoupling capacitor cell

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tapvpwrvgnd cell

10

Placement

 run_placement

11

magic -T /home/vsduser/Desktop/work/tool/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

12

13

DAY-3 lab: Designing Library cell and ngSPICE characterization

Cloning custom inverter standard cell design from github repository

 git clone https://github.com/nickson-jose/vsdstdcelldesign.git

1

Copying magic tech file to vsdstdcelldesign

 cp sky130A.tech /home/vsduser/Desktop/work/tool/openlane_working_dir/openplane/vsdstdcelldesign

2

3

custom CMOS inverter in magic tool

4

N-MOS in custom CMOS inverter in magic tool

5

P-MOS in custom CMOS inverter in magic tool

6

"A" is attached to locali in cell def sky130_inv

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"Y" is attached to locali in cell def sky130_inv

8

Poly-silicon in custom CMOS inverter in magic tool

9

Extracting CMOS inverter to SPICE characterization

 pwd
 extract all
 ext2spice cthresh 0 rthresh 0
 ext2spice

10

11

Opening SPICE extracted file

 vim sky130_inv.spice

12 Running and ploting the SPICE file

 ngspice sky130_inv.spice
 plot y vs time a

13

Rise time calculation

 Rise Time = T(80%)−T(20%)

80% of 3.3V = 2.64 14

20% of 3.3V = 0.660 15

 Rise Time = 0.05933ns

16

Fall time calculation

 Fall Time = T(80%)−T(20%)

80% of 3.3V = 2.64 17

20% of 3.3V = 0.660 18

  Fall Time = 0.02999ns

19

Rise propagation delay calculation

 Rise Delay= Tout(50%)​ − Tin(50%)​

50% of 3.3V = 1.65 20

 Rise propagation delay = 0.05639ns

21

Fall propagation delay calculation

 Fall Delay= Tout(50%)​ − Tin(50%)​

50% of 3.3V = 1.65 22

 Fall propagation delay = 0.0248ns

23

Introduction to magic tool options and steps to load sky130 DRC rules

Lab introduction to Magic and steps to load Sky130 tech-rules

 wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz
 tar xfz drc_tests.tgz
 cd drc_tests

24 To view .magicrc file

 gvim .magicrc

25

Open magic tool

 magic -d XR &

26

DRC check exercise

 load poly

27

poly.9

DRC rule for poly.9 in skywater130A pdk

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npolyres 29

poly 30

xpolyres 31

ppolyres 32

drc check
drc why

33 34 35

vi sky130A.tech

36

/drc

37

/poly.9

Error-1 38

Error-2 39

Error-2 (fixed) 40

Error-1 (fixed) 41

 tech load sky130A.tech
 drc check
 drc why

42

Poly.2

43

DRC rule for poly.2 in skywater130A pdk

44

Error 45

Error (fixed) 46

47

nwell.4

51

48

49

50

DAY-4 lab: Pre-layout timing analysis and importance of good clock tree

Open CMOS -inverter layout using magic tool

1

 press g on the layout for the grid formate

3

Generation of LEF file from layout

 Requirment_1.The input and output ports of the standard cell should lie on the intersection of the vertical and horizontal tracks.

2

 % grid 0.46um 0.34um 0.23um 0.17um

4 5

 Requirement_2: Width of the standard cell must be odd multiple of the Xpitch.

6

 Requriement_3: Hight of the standard cell must be even multiple of the Ypitch

7

Create port definition

8 9 10

Set port class and port use

11

Creating LEF file with same custom file name

 % write lef

12 13 14

copying sky130_vsdinv.lef from (openlane/vsdstdcelldesign) to (picorv32a/src)

 cp sky130_vsdinv.lef /home/Desktop/work/tool/openlane_working_dir/openlane/designs/picorv32a/src

15 16

copying sky130_fd_sc_hd_*.lib file from (openlane/vsdstdcelldesign/libs) to (picorv32a/src)

cp sky130_fd_sc_hd_* /home/Desktop/work/tool/openlane_working_dir/openlane/designs/picorv32a/src

17 18

Editing (config.tcl)

set ::env(LIB_SYNTH) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"
set ::env(LIB_FASTEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__fast.lib"
set ::env(LIB_SLOWEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__slow.lib"
set ::env(LIB_TYPICAL) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"

set ::env(EXTRA_LEFS) [glob $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/src/*.lef]

19

Plugging custom LEF to openlane flow

 docker
 ./flow.tcl -interactive
 package require openlane 0.9
 prep -design picorv32a -tag 08-09_14-03 -overwrite
 run_synthsis

20

 total negative slack (tns) = -711.59
 wrost negative slack (wns0 = -23.89

21

For reducing slack

 set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
 add_lefs -src $lefs
 echo $::env(SYNTH_STRATEGY)
 set ::env(SYNTH_STRATEGY) "DELAY 1"
 echo $::env(SYNTH_BUFFERING)
 echo $::env(SYNTH_SIZING)
 set ::env(SYNTH_SIZING) 1
 echo $::env(SYNTH_DRIVING_CELL)

22 23

 total negative slack (tns) = 0.00
 wrost negative slack (wns0 = 0.00

 run_floorplan
 run_placement

24

  magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

25

Expanding sky130_vsdinv custom block

   % expand

26 27

Create (pre_sta.conf) for STA analysis in openlane directory

28

Create (my_base.sdc) for STA analysis in openlane/designs/picorv32a/src

29

Output of pre_sta.conf is equal to synthesis stage

    sta pre_sta.conf

The slack is (7.14)

The slack should be greater than or equal to 0

   SLACK = (DATA REQUIRED TIME) - (DATA ARIVAL TIME)

30

Replace the old netlist with the newly generated netlist

 write_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/08-09_14-03/results/synthesis/picorv32a.synthesis.v

31 32

 run_floorplan
 run_placement

33

run_cts

34

Generated cts file

/home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/08-09_14-03/results/synthesis

35

Post-CTS timing analysis using OpenROAD

openroad

36

read_lef /openLANE_flow/designs/picorv32a/runs/08-09_14-03/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/08-09_14-03/results/cts/picorv32a.cts.def
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/08-09_14-03/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4

37 38

Post-CTS OpenROAD timing analysis by removing 'sky130_fd_sc_hd__clkbuf_1' cell from clock buffer list variable 'CTS_CLK_BUFFER_LIST'.

exit
echo $::env(CTS_CLK_BUFFER_LIST)
set ::env(CTS_CLK_BUFFER_LIST) [lreplace $::env(CTS_CLK_BUFFER_LIST) 0 0]
echo $::env(CTS_CLK_BUFFER_LIST)

39

echo $::env(CURRENT_DEF)
set ::env(CURRENT_DEF) /openLANE_flow/designs/picorv32a/runs/08-09_14-03/results/placement/picorv32a.placement.def

40

run_cts

41 42

echo $::env(CTS_CLK_BUFFER_LIST)
openroad
read_lef /openLANE_flow/designs/picorv32a/runs/08-09_14-03/tmp/merged.lef
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/08-09_14-03/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4

43 44 45

report_clock_skew -hold
report_clock_skew -setup

46

echo $::env(CTS_CLK_BUFFER_LIST)
set ::env(CTS_CLK_BUFFER_LIST) [linsert $::env(CTS_CLK_BUFFER_LIST) 0 sky130_fd_sc_hd__clkbuf_1]
echo $::env(CTS_CLK_BUFFER_LIST)

47

DAY-5 lab: Final steps for RTL2GDS using tritonRoute and openSTA

Power distibution network

docker
./flow.tcl -interactive
package require openlane 0.9
prep -design picorv32a
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
set ::env(SYNTH_STRATEGY) "DELAY 1"
set ::env(SYNTH_SIZING) 1
run_synthesis
init_floorplan
place_io
tap_decap_or
run_placement
run_cts
gen_pdn

1 2 3

Load PDN def in magic

 cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-09_05-11/tmp/floorplan/
 magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read 14-pdn.def &

4 5 6 7

Routing

echo $::env(CURRENT_DEF)
echo $::env(ROUTING_STRATEGY)
run_routing

8

0th optimization 9

57th optimization 10 11

Commands to load routed def in magic in another terminal

  cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-09_05-011/results/routing/
  magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.def &

13 14 15

fast route guide

  openlane/designs/picorv32a/runs/17-09_05-11/tmp/routing
  less 15-fastroute.guide

12

Post-Route parasitic extraction using SPEF extractor

  cd Desktop/work/tools/SPEF_EXTRACTOR
  python3 main.py /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-09_05-11/tmp/merged.lef /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-09_05-11/results/routing/picorv32a.def

Post-Route OpenSTA timing analysis with the extracted parasitics

docker
./flow.tcl -interactive
package require openlane 0.9
prep -design picorv32a -tag 17-09_05-11

openroad
read_lef /openLANE_flow/designs/picorv32a/runs/17-09_05-07/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/17-09_05-07/results/routing/picorv32a.def
write_db pico_route.db
read_db pico_route.db
read_verilog /openLANE_flow/designs/picorv32a/runs/17-09_05-07/results/synthesis/picorv32a.synthesis_preroute.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
read_spef /openLANE_flow/designs/picorv32a/runs/17-09_05-07/results/routing/picorv32a.spef
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4
exit

16 17 18

Acknowledgements