Refesh patches

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/008-0017-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch

@@ -36,7 +36,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 
 --- a/drivers/usb/dwc3/core.h
 +++ b/drivers/usb/dwc3/core.h
-@@ -258,6 +258,7 @@
+@@ -255,6 +255,7 @@
  /* Global User Control 1 Register */
  #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
  #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/008-0027-v5.19-drm-rockchip-Refactor-IOMMU-initialisation.patch

@@ -192,7 +192,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/94eee7ab434fe11eb0787f691e9f
  int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
 +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-@@ -2176,6 +2176,8 @@ static int vop_bind(struct device *dev,
+@@ -2189,6 +2189,8 @@ static int vop_bind(struct device *dev,
  		}
  	}
 

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/008-0048-v6.3-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k.patch

@@ -0,0 +1,32 @@
+From 64b69474edf3b885c19a89bb165f978ba1b4be00 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 10 Jan 2023 22:55:50 +0000
+Subject: [PATCH] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
+
+clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
+and not to 32 kHz on RK356x.
+
+Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
+to clk_rtc32k_frac.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -422,8 +422,9 @@
+ 		clock-names = "xin24m";
+ 		#clock-cells = <1>;
+ 		#reset-cells = <1>;
+-		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+-		assigned-clock-rates = <1200000000>, <200000000>;
++		assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
++		assigned-clock-rates = <32768>, <1200000000>, <200000000>;
++		assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
+ 		rockchip,grf = <&grf>;
+ 	};
+

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/008-0050-v6.6-clk-rockchip-rk3568-Add-PLL-rate-for-101MHz.patch

@@ -0,0 +1,26 @@
+From 7f890a885f9a226ae1309b967d4e6fac933610db Mon Sep 17 00:00:00 2001
+From: Alibek Omarov <a1ba.omarov@gmail.com>
+Date: Wed, 14 Jun 2023 16:47:16 +0300
+Subject: [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz
+
+This patch adds PLL setting for not so common resolution as 1920x720-50.00,
+which can be set using 2500 horizontal signals and 808 vertical.
+
+Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
+Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20230614134716.1055862-1-a1ba.omarov@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3568.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk
+ 	RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
+ 	RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
+ 	RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
++	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
+ 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/008-0051-v6.6-clk-rockchip-rk3568-Fix-PLL-rate-setting-for-78.75MHz.patch

@@ -0,0 +1,31 @@
+From dafebd0f9a4f56b10d7fbda0bff1f540d16a2ea4 Mon Sep 17 00:00:00 2001
+From: Alibek Omarov <a1ba.omarov@gmail.com>
+Date: Wed, 14 Jun 2023 16:47:50 +0300
+Subject: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
+
+PLL rate on RK356x is calculated through the simple formula:
+((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
+
+The PLL rate setting for 78.75MHz seems to be copied from 96MHz
+so this patch fixes it and configures it properly.
+
+Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
+Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
+Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20230614134750.1056293-1-a1ba.omarov@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3568.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk
+ 	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
+ 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+-	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
++	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
+ 	{ /* sentinel */ },
+ };

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/008-0052-v6.7-clk-rockchip-rk3568-Add-PLL-rate-for-292.5MHz.patch

@@ -0,0 +1,29 @@
+From 1af27671f62ce919f1fb76082ed81f71cb090989 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Wed, 18 Oct 2023 10:33:55 -0500
+Subject: [PATCH] clk: rockchip: rk3568: Add PLL rate for 292.5MHz
+
+Add support for a PLL rate of 292.5MHz so that the Powkiddy RGB30 panel
+can run at a requested 60hz (59.96, close enough).
+
+I have confirmed this rate fits with all the constraints
+listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
+2 Clock & Reset Unit (CRU)."
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20231018153357.343142-2-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3568.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -72,6 +72,7 @@ static struct rockchip_pll_rate_table rk
+ 	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ 	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ 	RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
++	RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0),
+ 	RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
+ 	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ 	RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/024-v6.4-arm64-dts-rockchip-Fix-rk356x-PCIe-register-and-range-map.patch

@@ -54,7 +54,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  		reset-names = "pipe";
 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -855,7 +855,7 @@
+@@ -856,7 +856,7 @@
  		compatible = "rockchip,rk3568-pcie";
  		reg = <0x3 0xc0000000 0x0 0x00400000>,
  		      <0x0 0xfe260000 0x0 0x00010000>,
@@ -63,7 +63,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  		reg-names = "dbi", "apb", "config";
  		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
  			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
-@@ -884,8 +884,9 @@
+@@ -885,8 +885,9 @@
  		phys = <&combphy2 PHY_TYPE_PCIE>;
  		phy-names = "pcie-phy";
  		power-domains = <&power RK3568_PD_PIPE>;

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/025-02-v6.3-mmc-sdhci-of-dwcmshc-enable-host-V4-support-for-BlueField.patch

@@ -0,0 +1,32 @@
+From 95921151e04335e9e2ddf4f294405e64be4ea947 Mon Sep 17 00:00:00 2001
+From: Liming Sun <limings@nvidia.com>
+Date: Wed, 11 Jan 2023 13:14:58 -0500
+Subject: [PATCH] mmc: sdhci-of-dwcmshc: enable host V4 support for BlueField-3
+ SoC
+
+This commit enables SDHCI Host V4 support on Bluefield-3 SoC to be
+consistent with the default setting in firmware(UEFI).
+
+Reviewed-by: David Woods <davwoods@nvidia.com>
+Signed-off-by: Liming Sun <limings@nvidia.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/990885f566c32ac8e6888ad6b434fb70d1a5d7af.1673460632.git.limings@nvidia.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -528,6 +528,11 @@ static int dwcmshc_probe(struct platform
+ 			goto err_clk;
+ 	}
+
++#ifdef CONFIG_ACPI
++	if (pltfm_data == &sdhci_dwcmshc_bf3_pdata)
++		sdhci_enable_v4_mode(host);
++#endif
++
+ 	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+
+ 	err = sdhci_setup_host(host);

openwrt-23.05/patches/target/linux/rockchip/patches-5.15/025-04-v6.3-mmc-sdhci-of-dwcmshc-add-the-missing-device-table-IDs-for.patch

@@ -0,0 +1,27 @@
+From cfd4ea4815d16f7426723a5cb80ee5db811ea1f2 Mon Sep 17 00:00:00 2001
+From: Liming Sun <limings@nvidia.com>
+Date: Thu, 2 Feb 2023 10:29:15 -0500
+Subject: [PATCH] mmc: sdhci-of-dwcmshc: add the missing device table IDs for
+ acpi
+
+This commit adds the missing MODULE_DEVICE_TABLE for acpi, or else
+it won't be loaded automatically when compiled as a kernel module.
+
+Reviewed-by: David Thompson <davthompson@nvidia.com>
+Signed-off-by: Liming Sun <limings@nvidia.com>
+Link: https://lore.kernel.org/r/f57ad0f8fdf663465bca74467c344dfa305a3199.1675305696.git.limings@nvidia.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -451,6 +451,7 @@ static const struct acpi_device_id sdhci
+ 	},
+ 	{}
+ };
++MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids);
+ #endif
+
+ static int dwcmshc_probe(struct platform_device *pdev)