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ARM: Don't rewrite blcc default jumpkind (#441)
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* ARM: Don't rewrite blcc default jumpkind

* [pre-commit.ci] auto fixes from pre-commit.com hooks

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Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
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mborgerson and pre-commit-ci[bot] authored Dec 12, 2024
1 parent 655b83c commit a7a6b99
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Showing 2 changed files with 16 additions and 1 deletion.
2 changes: 1 addition & 1 deletion pyvex_c/postprocess.c
Original file line number Diff line number Diff line change
Expand Up @@ -237,7 +237,7 @@ void arm_post_processor_determine_calls(
// Fix the not-default exit
other_exit->Ist.Exit.jk = Ijk_Call;
}
else {
else if (!has_exit || other_exit->Ist.Exit.jk != Ijk_Call) {
//Fix the default exit
irsb->jumpkind = Ijk_Call;
}
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15 changes: 15 additions & 0 deletions tests/test_arm_postprocess.py
Original file line number Diff line number Diff line change
Expand Up @@ -314,6 +314,21 @@ def test_arm_postprocess_call():
)
assert irsb.jumpkind == "Ijk_Call"

# 400000 str lr, [sp,#-0x4]!
# 400004 mov r1, #0xa
# 400008 cmp r0, r1
# 40000c blne #FunctionB
irsb = pyvex.IRSB(
data=bytes.fromhex("04e02de50a10a0e3010050e10100001b"),
mem_addr=0x400000,
arch=pyvex.ARCH_ARM_LE,
num_inst=4,
opt_level=i,
)
assert len(irsb.exit_statements) == 1
assert irsb.exit_statements[0][2].jumpkind == "Ijk_Call"
assert irsb.jumpkind == "Ijk_Boring"


def test_arm_postprocess_ret():
for i in range(3):
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