diff --git a/src/ansys/aedt/core/hfss3dlayout.py b/src/ansys/aedt/core/hfss3dlayout.py index ca3b0b85346..307ffd1f82a 100644 --- a/src/ansys/aedt/core/hfss3dlayout.py +++ b/src/ansys/aedt/core/hfss3dlayout.py @@ -2292,13 +2292,12 @@ def find_scale(data, header_line): self.oboundary.EditExcitations( [ "NAME:Excitations", - [source, f"pwl({ds_name_mag}, Freq)", f"pwl({ds_name_phase}, Freq)"], + [source, f"pwl({ds_name_phase}, Freq)", f"pwl({ds_name_mag}, Freq)"], ], ["NAME:Terminations", [source, False, str(impedance) + "ohm", "0ohm"]], ",".join(str_val), [], ) - self.logger.info("Source Excitation updated with Dataset.") return True self.logger.error("Port not found.") diff --git a/src/ansys/aedt/core/workflows/hfss3dlayout/images/large/push.png b/src/ansys/aedt/core/workflows/hfss3dlayout/images/large/push.png new file mode 100644 index 00000000000..2eb7c639efb Binary files /dev/null and b/src/ansys/aedt/core/workflows/hfss3dlayout/images/large/push.png differ diff --git a/tests/system/general/test_41_3dlayout_modeler.py b/tests/system/general/test_41_3dlayout_modeler.py index d05fafd4e00..cc4260d976b 100644 --- a/tests/system/general/test_41_3dlayout_modeler.py +++ b/tests/system/general/test_41_3dlayout_modeler.py @@ -336,6 +336,7 @@ def test_13a_create_edge_port(self): assert self.aedtapp.create_edge_port("line1", 3, False) assert len(self.aedtapp.excitations) > 0 time_domain = os.path.join(TESTS_GENERAL_PATH, "example_models", test_subfolder, "Sinusoidal.csv") + assert self.aedtapp.boundaries[0].object_properties.props["Magnitude"] == "1V" assert self.aedtapp.edit_source_from_file( source=port_wave.name, input_file=time_domain, @@ -344,6 +345,7 @@ def test_13a_create_edge_port(self): y_scale=1e-3, data_format="Voltage", ) + assert self.aedtapp.boundaries[0].object_properties.props["Magnitude"] != "1V" self.aedtapp.boundaries[0].object_properties.props["Boundary Type"] = "PEC" assert list(self.aedtapp.oboundary.GetAllBoundariesList())[0] == self.aedtapp.boundaries[0].name