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dvb_dma_hw.tcl
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dvb_dma_hw.tcl
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# NetUP Universal Dual DVB-CI FPGA firmware
# http://www.netup.tv
#
# Copyright (c) 2014 NetUP Inc, AVB Labs
# License: GPLv3
# TCL File Generated by Component Editor 11.1sp2
# Sun Apr 13 16:50:46 MSD 2014
# DO NOT MODIFY
# +-----------------------------------
# |
# | dvb_dma "dvb_dma" v1.0
# | AVB 2014.04.13.16:50:46
# |
# |
# |
# | ./avblabs_common_pkg.vhd syn, sim
# | ./dvb_dma_fifo_ram.vhd syn, sim
# | ./dvb_dma.vhd syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | request TCL package from ACDS 11.0
# |
package require -exact sopc 11.0
# |
# +-----------------------------------
# +-----------------------------------
# | module dvb_dma
# |
set_module_property NAME dvb_dma
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR AVB
set_module_property DISPLAY_NAME dvb_dma
set_module_property TOP_LEVEL_HDL_FILE dvb_dma.vhd
set_module_property TOP_LEVEL_HDL_MODULE dvb_dma
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
set_module_property STATIC_TOP_LEVEL_MODULE_NAME dvb_dma
set_module_property FIX_110_VIP_PATH false
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file avblabs_common_pkg.vhd {SYNTHESIS SIMULATION}
add_file dvb_dma_fifo_ram.vhd {SYNTHESIS SIMULATION}
add_file dvb_dma.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point avalon_slave_0
# |
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset_sink
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitStates 0
set_interface_property avalon_slave_0 readWaitTime 0
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
add_interface_port avalon_slave_0 address address Input 4
add_interface_port avalon_slave_0 byteenable byteenable Input 4
add_interface_port avalon_slave_0 writedata writedata Input 32
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 readdata readdata Output 32
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clock
# |
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
add_interface_port clock clk clk Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point conduit_end
# |
add_interface conduit_end conduit end
set_interface_property conduit_end ENABLED true
add_interface_port conduit_end dvb_sop export Input 1
add_interface_port conduit_end dvb_data export Input 8
add_interface_port conduit_end dvb_dval export Input 1
add_interface_port conduit_end mem_size export Output 7
add_interface_port conduit_end mem_addr export Output 61
add_interface_port conduit_end mem_byteen export Output 8
add_interface_port conduit_end mem_wrdata export Output 64
add_interface_port conduit_end mem_write export Output 1
add_interface_port conduit_end mem_waitreq export Input 1
add_interface_port conduit_end interrupt export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point reset_sink
# |
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
add_interface_port reset_sink rst reset Input 1
# |
# +-----------------------------------