pcie_compiler_0_core.vhd

-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
-- 
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3

-- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 259]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2014 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

library IEEE;
use IEEE.std_logic_1164.all;

ENTITY pcie_compiler_0_core IS
	PORT (
		AvlClk_i	: IN STD_LOGIC;
		CraAddress_i	: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		CraByteEnable_i	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		CraChipSelect_i	: IN STD_LOGIC;
		CraRead	: IN STD_LOGIC;
		CraWrite	: IN STD_LOGIC;
		CraWriteData_i	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		Rstn_i	: IN STD_LOGIC;
		RxmIrqNum_i	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		RxmIrq_i	: IN STD_LOGIC;
		RxmReadDataValid_i	: IN STD_LOGIC;
		RxmReadData_i	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		RxmWaitRequest_i	: IN STD_LOGIC;
		TxsAddress_i	: IN STD_LOGIC_VECTOR (27 DOWNTO 0);
		TxsBurstCount_i	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		TxsByteEnable_i	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		TxsChipSelect_i	: IN STD_LOGIC;
		TxsRead_i	: IN STD_LOGIC;
		TxsWriteData_i	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		TxsWrite_i	: IN STD_LOGIC;
		aer_msi_num	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		app_int_sts	: IN STD_LOGIC;
		app_msi_num	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		app_msi_req	: IN STD_LOGIC;
		app_msi_tc	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		core_clk_in	: IN STD_LOGIC;
		cpl_err	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		cpl_pending	: IN STD_LOGIC;
		crst	: IN STD_LOGIC;
		hpg_ctrler	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		lmi_addr	: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		lmi_din	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		lmi_rden	: IN STD_LOGIC;
		lmi_wren	: IN STD_LOGIC;
		npor	: IN STD_LOGIC;
		pclk_central	: IN STD_LOGIC;
		pclk_ch0	: IN STD_LOGIC;
		pex_msi_num	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		pld_clk	: IN STD_LOGIC;
		pll_fixed_clk	: IN STD_LOGIC;
		pm_auxpwr	: IN STD_LOGIC;
		pm_data	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		pm_event	: IN STD_LOGIC;
		pme_to_cr	: IN STD_LOGIC;
		rc_areset	: IN STD_LOGIC;
		rc_inclk_eq_125mhz	: IN STD_LOGIC;
		rc_pll_locked	: IN STD_LOGIC;
		rc_rx_pll_locked_one	: IN STD_LOGIC;
		rx_st_mask0	: IN STD_LOGIC;
		rx_st_ready0	: IN STD_LOGIC;
		srst	: IN STD_LOGIC;
		test_in	: IN STD_LOGIC_VECTOR (39 DOWNTO 0);
		tx_st_data0	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		tx_st_data0_p1	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		tx_st_eop0	: IN STD_LOGIC;
		tx_st_eop0_p1	: IN STD_LOGIC;
		tx_st_err0	: IN STD_LOGIC;
		tx_st_sop0	: IN STD_LOGIC;
		tx_st_sop0_p1	: IN STD_LOGIC;
		tx_st_valid0	: IN STD_LOGIC;
		phystatus0_ext	: IN STD_LOGIC;
		rxdata0_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak0_ext	: IN STD_LOGIC;
		rxelecidle0_ext	: IN STD_LOGIC;
		rxstatus0_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid0_ext	: IN STD_LOGIC;
		CraIrq_o	: OUT STD_LOGIC;
		CraReadData_o	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		CraWaitRequest_o	: OUT STD_LOGIC;
		RxmAddress_o	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		RxmBurstCount_o	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		RxmByteEnable_o	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		RxmRead_o	: OUT STD_LOGIC;
		RxmWriteData_o	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		RxmWrite_o	: OUT STD_LOGIC;
		TxsReadDataValid_o	: OUT STD_LOGIC;
		TxsReadData_o	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		TxsWaitRequest_o	: OUT STD_LOGIC;
		app_int_ack	: OUT STD_LOGIC;
		app_msi_ack	: OUT STD_LOGIC;
		avs_pcie_reconfig_readdata	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		avs_pcie_reconfig_readdatavalid	: OUT STD_LOGIC;
		avs_pcie_reconfig_waitrequest	: OUT STD_LOGIC;
		core_clk_out	: OUT STD_LOGIC;
		derr_cor_ext_rcv0	: OUT STD_LOGIC;
		derr_cor_ext_rpl	: OUT STD_LOGIC;
		derr_rpl	: OUT STD_LOGIC;
		dl_ltssm	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
		dlup_exit	: OUT STD_LOGIC;
		eidle_infer_sel	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
		ev_128ns	: OUT STD_LOGIC;
		ev_1us	: OUT STD_LOGIC;
		hip_extraclkout	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		hotrst_exit	: OUT STD_LOGIC;
		int_status	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		l2_exit	: OUT STD_LOGIC;
		lane_act	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		lmi_ack	: OUT STD_LOGIC;
		lmi_dout	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		npd_alloc_1cred_vc0	: OUT STD_LOGIC;
		npd_cred_vio_vc0	: OUT STD_LOGIC;
		nph_alloc_1cred_vc0	: OUT STD_LOGIC;
		nph_cred_vio_vc0	: OUT STD_LOGIC;
		pme_to_sr	: OUT STD_LOGIC;
		r2c_err0	: OUT STD_LOGIC;
		rate_ext	: OUT STD_LOGIC;
		rc_gxb_powerdown	: OUT STD_LOGIC;
		rc_rx_analogreset	: OUT STD_LOGIC;
		rc_rx_digitalreset	: OUT STD_LOGIC;
		rc_tx_digitalreset	: OUT STD_LOGIC;
		reset_status	: OUT STD_LOGIC;
		rx_fifo_empty0	: OUT STD_LOGIC;
		rx_fifo_full0	: OUT STD_LOGIC;
		rx_st_bardec0	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_be0	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_be0_p1	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_data0	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		rx_st_data0_p1	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		rx_st_eop0	: OUT STD_LOGIC;
		rx_st_eop0_p1	: OUT STD_LOGIC;
		rx_st_err0	: OUT STD_LOGIC;
		rx_st_sop0	: OUT STD_LOGIC;
		rx_st_sop0_p1	: OUT STD_LOGIC;
		rx_st_valid0	: OUT STD_LOGIC;
		serr_out	: OUT STD_LOGIC;
		suc_spd_neg	: OUT STD_LOGIC;
		swdn_wake	: OUT STD_LOGIC;
		swup_hotrst	: OUT STD_LOGIC;
		test_out	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		tl_cfg_add	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		tl_cfg_ctl	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		tl_cfg_ctl_wr	: OUT STD_LOGIC;
		tl_cfg_sts	: OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
		tl_cfg_sts_wr	: OUT STD_LOGIC;
		tx_cred0	: OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
		tx_deemph	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		tx_fifo_empty0	: OUT STD_LOGIC;
		tx_fifo_full0	: OUT STD_LOGIC;
		tx_fifo_rdptr0	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		tx_fifo_wrptr0	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		tx_margin	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
		tx_st_ready0	: OUT STD_LOGIC;
		use_pcie_reconfig	: OUT STD_LOGIC;
		wake_oen	: OUT STD_LOGIC;
		powerdown0_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity0_ext	: OUT STD_LOGIC;
		txcompl0_ext	: OUT STD_LOGIC;
		txdata0_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak0_ext	: OUT STD_LOGIC;
		txdetectrx0_ext	: OUT STD_LOGIC;
		txelecidle0_ext	: OUT STD_LOGIC
	);
END pcie_compiler_0_core;

ARCHITECTURE SYN OF pcie_compiler_0_core IS

	SIGNAL signal_wire0	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire1	:  STD_LOGIC;
	SIGNAL signal_wire2	:  STD_LOGIC;
	SIGNAL signal_wire3	:  STD_LOGIC;
	SIGNAL signal_wire4	:  STD_LOGIC;
	SIGNAL signal_wire5	:  STD_LOGIC;
	SIGNAL signal_wire6	:  STD_LOGIC_VECTOR (15 DOWNTO 0);
	SIGNAL signal_wire7	:  STD_LOGIC_VECTOR (1 DOWNTO 0);
	SIGNAL signal_wire8	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire9	:  STD_LOGIC_VECTOR (6 DOWNTO 0);
	SIGNAL signal_wire10	:  STD_LOGIC;
	SIGNAL signal_wire11	:  STD_LOGIC;
	SIGNAL signal_wire12	:  STD_LOGIC;
	SIGNAL signal_wire13	:  STD_LOGIC_VECTOR (12 DOWNTO 0);
	SIGNAL signal_wire14	:  STD_LOGIC_VECTOR (11 DOWNTO 0);
	SIGNAL signal_wire15	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire16	:  STD_LOGIC;
	SIGNAL signal_wire17	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire18	:  STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL signal_wire19	:  STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL signal_wire20	:  STD_LOGIC;
	SIGNAL signal_wire21	:  STD_LOGIC;
	SIGNAL signal_wire22	:  STD_LOGIC;
	SIGNAL signal_wire23	:  STD_LOGIC;
	SIGNAL signal_wire24	:  STD_LOGIC;
	SIGNAL signal_wire25	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire26	:  STD_LOGIC;
	SIGNAL signal_wire27	:  STD_LOGIC_VECTOR (1 DOWNTO 0);
	SIGNAL signal_wire28	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire29	:  STD_LOGIC_VECTOR (23 DOWNTO 0);
	SIGNAL signal_wire30	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire31	:  STD_LOGIC;
	SIGNAL signal_wire32	:  STD_LOGIC;
	SIGNAL signal_wire33	:  STD_LOGIC_VECTOR (63 DOWNTO 0);
	SIGNAL signal_wire34	:  STD_LOGIC_VECTOR (63 DOWNTO 0);
	SIGNAL signal_wire35	:  STD_LOGIC;
	SIGNAL signal_wire36	:  STD_LOGIC;
	SIGNAL signal_wire37	:  STD_LOGIC;
	SIGNAL signal_wire38	:  STD_LOGIC;
	SIGNAL signal_wire39	:  STD_LOGIC;
	SIGNAL signal_wire40	:  STD_LOGIC;
	SIGNAL signal_wire41	:  STD_LOGIC;
	SIGNAL signal_wire42	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire43	:  STD_LOGIC;
	SIGNAL signal_wire44	:  STD_LOGIC;
	SIGNAL signal_wire45	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire46	:  STD_LOGIC;
	SIGNAL signal_wire47	:  STD_LOGIC;
	SIGNAL signal_wire48	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire49	:  STD_LOGIC;
	SIGNAL signal_wire50	:  STD_LOGIC;
	SIGNAL signal_wire51	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire52	:  STD_LOGIC;
	SIGNAL signal_wire53	:  STD_LOGIC;
	SIGNAL signal_wire54	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire55	:  STD_LOGIC;
	SIGNAL signal_wire56	:  STD_LOGIC;
	SIGNAL signal_wire57	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire58	:  STD_LOGIC;
	SIGNAL signal_wire59	:  STD_LOGIC;
	SIGNAL signal_wire60	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire61	:  STD_LOGIC;
	SIGNAL signal_wire62	:  STD_LOGIC;
	SIGNAL signal_wire63	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire64	:  STD_LOGIC;
	SIGNAL signal_wire65	:  STD_LOGIC;
	SIGNAL signal_wire66	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire67	:  STD_LOGIC;
	SIGNAL signal_wire68	:  STD_LOGIC;
	SIGNAL signal_wire69	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire70	:  STD_LOGIC;
	SIGNAL signal_wire71	:  STD_LOGIC;
	SIGNAL signal_wire72	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire73	:  STD_LOGIC;
	SIGNAL signal_wire74	:  STD_LOGIC;
	SIGNAL signal_wire75	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire76	:  STD_LOGIC;
	SIGNAL signal_wire77	:  STD_LOGIC;
	SIGNAL signal_wire78	:  STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL signal_wire79	:  STD_LOGIC;
	SIGNAL signal_wire80	:  STD_LOGIC;
	SIGNAL signal_wire81	:  STD_LOGIC_VECTOR (2 DOWNTO 0);
	SIGNAL signal_wire82	:  STD_LOGIC;

	COMPONENT altpcie_hip_pipen1b
	GENERIC (
		tx_cdc_full_value	: NATURAL;
		CB_PCIE_MODE	: NATURAL;
		CG_AVALON_S_ADDR_WIDTH	: NATURAL;
		CG_COMMON_CLOCK_MODE	: NATURAL;
		CG_IMPL_CRA_AV_SLAVE_PORT	: NATURAL;
		INTENDED_DEVICE_FAMILY	: STRING;
		CB_A2P_ADDR_MAP_NUM_ENTRIES	: NATURAL;
		CB_A2P_ADDR_MAP_PASS_THRU_BITS	: NATURAL;
		CB_A2P_ADDR_MAP_IS_FIXED	: NATURAL;
		CB_A2P_ADDR_MAP_FIXED_TABLE	: STD_LOGIC_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000";
		CB_P2A_AVALON_ADDR_B0	: STD_LOGIC_VECTOR := X"00000000";
		CB_P2A_AVALON_ADDR_B1	: STD_LOGIC_VECTOR := X"00040000";
		CB_P2A_AVALON_ADDR_B2	: STD_LOGIC_VECTOR := X"00000000";
		CB_P2A_AVALON_ADDR_B3	: STD_LOGIC_VECTOR := X"00000000";
		CB_P2A_AVALON_ADDR_B4	: STD_LOGIC_VECTOR := X"00000000";
		CB_P2A_AVALON_ADDR_B5	: STD_LOGIC_VECTOR := X"00000000";
		TL_SELECTION 	: NATURAL;
		bypass_tl	: STRING;
		AST_LITE	: NATURAL;
		p_pcie_hip_type	: STRING;
		retry_buffer_last_active_address	: STRING;
		advanced_errors	: STRING;
		bar0_io_space	: STRING;
		bar0_64bit_mem_space	: STRING;
		bar0_prefetchable	: STRING;
		bar0_size_mask	: NATURAL;
		bar1_io_space	: STRING;
		bar1_64bit_mem_space	: STRING;
		bar1_prefetchable	: STRING;
		bar1_size_mask	: NATURAL;
		enable_ecrc_check	: STRING;
		enable_ecrc_gen	: STRING;
		enable_l1_aspm	: STRING;
		l01_entry_latency	: NATURAL;
		core_clk_source 	: STRING;
		pcie_mode	: STRING;
		expansion_base_address_register	: NATURAL;
		extend_tag_field	: STRING;
		bypass_cdc	: STRING;
		vc_arbitration	: NATURAL;
		no_soft_reset	: STRING;
		enable_ch0_pclk_out	: STRING;
		core_clk_divider	: NATURAL;
		millisecond_cycle_count	: NATURAL;
		single_rx_detect	: NATURAL;
		enable_coreclk_out_half_rate	: STRING;
		enable_gen2_core	: STRING;
		gen2_lane_rate_mode	: STRING;
		lane_mask	: STD_LOGIC_VECTOR := B"11111110";
		max_link_width	: NATURAL;
		vendor_id	: NATURAL;
		device_id	: NATURAL;
		revision_id	: NATURAL;
		class_code	: NATURAL;
		subsystem_vendor_id	: NATURAL;
		subsystem_device_id	: NATURAL;
		port_link_number	: NATURAL;
		vc_enable	: STD_LOGIC_VECTOR := B"0000000";
		vc1_clk_enable	: STRING;
		low_priority_vc	: NATURAL;
		max_payload_size	: NATURAL;
		msi_function_count	: NATURAL;
		endpoint_l0_latency	: NATURAL;
		endpoint_l1_latency	: NATURAL;
		diffclock_nfts_count	: NATURAL;
		sameclock_nfts_count	: NATURAL;
		l1_exit_latency_sameclock	: NATURAL;
		l1_exit_latency_diffclock	: NATURAL;
		l0_exit_latency_sameclock	: NATURAL;
		l0_exit_latency_diffclock	: NATURAL;
		enable_msi_64bit_addressing	: STRING;
		gen2_diffclock_nfts_count	: NATURAL;
		gen2_sameclock_nfts_count	: NATURAL;
		enable_function_msix_support	: STRING;
		credit_buffer_allocation_aux	: STRING;
		eie_before_nfts_count	: NATURAL;
		enable_completion_timeout_disable	: STRING;
		completion_timeout	: STRING;
		enable_adapter_half_rate_mode	: STRING;
		msix_pba_bir	: NATURAL;
		msix_pba_offset	: NATURAL;
		msix_table_bir	: NATURAL;
		msix_table_offset	: NATURAL;
		msix_table_size	: NATURAL;
		use_crc_forwarding	: STRING;
		surprise_down_error_support	: STRING;
		dll_active_report_support	: STRING;
		bar_io_window_size	: STRING;
		bar_prefetchable	: NATURAL;
		hot_plug_support	: STD_LOGIC_VECTOR := B"0000000";
		no_command_completed	: STRING;
		slot_power_limit	: NATURAL;
		slot_power_scale	: NATURAL;
		slot_number	: NATURAL;
		enable_slot_register	: STRING;
		vc0_rx_flow_ctrl_posted_header	: NATURAL;
		vc0_rx_flow_ctrl_posted_data	: NATURAL;
		vc0_rx_flow_ctrl_nonposted_header	: NATURAL;
		vc0_rx_flow_ctrl_nonposted_data	: NATURAL;
		vc0_rx_flow_ctrl_compl_header	: NATURAL;
		vc0_rx_flow_ctrl_compl_data	: NATURAL;
		RX_BUF	: NATURAL;
		RH_NUM	: NATURAL;
		G_TAG_NUM0 	: NATURAL
	);
	PORT (
		AvlClk_i	: IN STD_LOGIC;
		CraAddress_i	: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		CraByteEnable_i	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		CraChipSelect_i	: IN STD_LOGIC;
		CraRead	: IN STD_LOGIC;
		CraWrite	: IN STD_LOGIC;
		CraWriteData_i	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		Rstn_i	: IN STD_LOGIC;
		RxmIrqNum_i	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		RxmIrq_i	: IN STD_LOGIC;
		RxmReadDataValid_i	: IN STD_LOGIC;
		RxmReadData_i	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		RxmWaitRequest_i	: IN STD_LOGIC;
		TxsAddress_i	: IN STD_LOGIC_VECTOR (27 DOWNTO 0);
		TxsBurstCount_i	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		TxsByteEnable_i	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		TxsChipSelect_i	: IN STD_LOGIC;
		TxsRead_i	: IN STD_LOGIC;
		TxsWriteData_i	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		TxsWrite_i	: IN STD_LOGIC;
		aer_msi_num	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		app_int_sts	: IN STD_LOGIC;
		app_msi_num	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		app_msi_req	: IN STD_LOGIC;
		app_msi_tc	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		avs_pcie_reconfig_address	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		avs_pcie_reconfig_chipselect	: IN STD_LOGIC;
		avs_pcie_reconfig_clk	: IN STD_LOGIC;
		avs_pcie_reconfig_read	: IN STD_LOGIC;
		avs_pcie_reconfig_rstn	: IN STD_LOGIC;
		avs_pcie_reconfig_write	: IN STD_LOGIC;
		avs_pcie_reconfig_writedata	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		core_clk_in	: IN STD_LOGIC;
		cpl_err	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		cpl_pending	: IN STD_LOGIC;
		crst	: IN STD_LOGIC;
		hpg_ctrler	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		lmi_addr	: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		lmi_din	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		lmi_rden	: IN STD_LOGIC;
		lmi_wren	: IN STD_LOGIC;
		mode	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		npor	: IN STD_LOGIC;
		pclk_central	: IN STD_LOGIC;
		pclk_ch0	: IN STD_LOGIC;
		pex_msi_num	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		pld_clk	: IN STD_LOGIC;
		pll_fixed_clk	: IN STD_LOGIC;
		pm_auxpwr	: IN STD_LOGIC;
		pm_data	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		pm_event	: IN STD_LOGIC;
		pme_to_cr	: IN STD_LOGIC;
		rc_areset	: IN STD_LOGIC;
		rc_inclk_eq_125mhz	: IN STD_LOGIC;
		rc_pll_locked	: IN STD_LOGIC;
		rc_rx_pll_locked_one	: IN STD_LOGIC;
		rx_st_mask0	: IN STD_LOGIC;
		rx_st_ready0	: IN STD_LOGIC;
		srst	: IN STD_LOGIC;
		swdn_in	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		swup_in	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		test_in	: IN STD_LOGIC_VECTOR (39 DOWNTO 0);
		tl_slotclk_cfg	: IN STD_LOGIC;
		tlbp_dl_aspm_cr0	: IN STD_LOGIC;
		tlbp_dl_comclk_reg	: IN STD_LOGIC;
		tlbp_dl_ctrl_link2	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		tlbp_dl_data_upfc	: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		tlbp_dl_hdr_upfc	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		tlbp_dl_inh_dllp	: IN STD_LOGIC;
		tlbp_dl_maxpload_dcr	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		tlbp_dl_req_phycfg	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		tlbp_dl_req_phypm	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		tlbp_dl_req_upfc	: IN STD_LOGIC;
		tlbp_dl_req_wake	: IN STD_LOGIC;
		tlbp_dl_rx_ecrcchk	: IN STD_LOGIC;
		tlbp_dl_snd_upfc	: IN STD_LOGIC;
		tlbp_dl_tx_reqpm	: IN STD_LOGIC;
		tlbp_dl_tx_typpm	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		tlbp_dl_txcfg_extsy	: IN STD_LOGIC;
		tlbp_dl_typ_upfc	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		tlbp_dl_vc_ctrl	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		tlbp_dl_vcid_map	: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
		tlbp_dl_vcid_upfc	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		tx_st_data0	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		tx_st_data0_p1	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		tx_st_eop0	: IN STD_LOGIC;
		tx_st_eop0_p1	: IN STD_LOGIC;
		tx_st_err0	: IN STD_LOGIC;
		tx_st_sop0	: IN STD_LOGIC;
		tx_st_sop0_p1	: IN STD_LOGIC;
		tx_st_valid0	: IN STD_LOGIC;
		rx_st_mask1	: IN STD_LOGIC;
		rx_st_ready1	: IN STD_LOGIC;
		tx_st_data1	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		tx_st_data1_p1	: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		tx_st_eop1	: IN STD_LOGIC;
		tx_st_eop1_p1	: IN STD_LOGIC;
		tx_st_err1	: IN STD_LOGIC;
		tx_st_sop1	: IN STD_LOGIC;
		tx_st_sop1_p1	: IN STD_LOGIC;
		tx_st_valid1	: IN STD_LOGIC;
		phystatus0_ext	: IN STD_LOGIC;
		rxdata0_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak0_ext	: IN STD_LOGIC;
		rxelecidle0_ext	: IN STD_LOGIC;
		rxstatus0_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid0_ext	: IN STD_LOGIC;
		phystatus1_ext	: IN STD_LOGIC;
		rxdata1_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak1_ext	: IN STD_LOGIC;
		rxelecidle1_ext	: IN STD_LOGIC;
		rxstatus1_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid1_ext	: IN STD_LOGIC;
		phystatus2_ext	: IN STD_LOGIC;
		rxdata2_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak2_ext	: IN STD_LOGIC;
		rxelecidle2_ext	: IN STD_LOGIC;
		rxstatus2_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid2_ext	: IN STD_LOGIC;
		phystatus3_ext	: IN STD_LOGIC;
		rxdata3_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak3_ext	: IN STD_LOGIC;
		rxelecidle3_ext	: IN STD_LOGIC;
		rxstatus3_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid3_ext	: IN STD_LOGIC;
		phystatus4_ext	: IN STD_LOGIC;
		rxdata4_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak4_ext	: IN STD_LOGIC;
		rxelecidle4_ext	: IN STD_LOGIC;
		rxstatus4_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid4_ext	: IN STD_LOGIC;
		phystatus5_ext	: IN STD_LOGIC;
		rxdata5_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak5_ext	: IN STD_LOGIC;
		rxelecidle5_ext	: IN STD_LOGIC;
		rxstatus5_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid5_ext	: IN STD_LOGIC;
		phystatus6_ext	: IN STD_LOGIC;
		rxdata6_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak6_ext	: IN STD_LOGIC;
		rxelecidle6_ext	: IN STD_LOGIC;
		rxstatus6_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid6_ext	: IN STD_LOGIC;
		phystatus7_ext	: IN STD_LOGIC;
		rxdata7_ext	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak7_ext	: IN STD_LOGIC;
		rxelecidle7_ext	: IN STD_LOGIC;
		rxstatus7_ext	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid7_ext	: IN STD_LOGIC;
		CraIrq_o	: OUT STD_LOGIC;
		CraReadData_o	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		CraWaitRequest_o	: OUT STD_LOGIC;
		RxmAddress_o	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		RxmBurstCount_o	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		RxmByteEnable_o	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		RxmRead_o	: OUT STD_LOGIC;
		RxmWriteData_o	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		RxmWrite_o	: OUT STD_LOGIC;
		TxsReadDataValid_o	: OUT STD_LOGIC;
		TxsReadData_o	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		TxsWaitRequest_o	: OUT STD_LOGIC;
		app_int_ack	: OUT STD_LOGIC;
		app_msi_ack	: OUT STD_LOGIC;
		avs_pcie_reconfig_readdata	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		avs_pcie_reconfig_readdatavalid	: OUT STD_LOGIC;
		avs_pcie_reconfig_waitrequest	: OUT STD_LOGIC;
		core_clk_out	: OUT STD_LOGIC;
		derr_cor_ext_rcv0	: OUT STD_LOGIC;
		derr_cor_ext_rpl	: OUT STD_LOGIC;
		derr_rpl	: OUT STD_LOGIC;
		dl_ltssm	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
		dlup_exit	: OUT STD_LOGIC;
		eidle_infer_sel	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
		ev_128ns	: OUT STD_LOGIC;
		ev_1us	: OUT STD_LOGIC;
		hip_extraclkout	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		hotrst_exit	: OUT STD_LOGIC;
		int_status	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		l2_exit	: OUT STD_LOGIC;
		lane_act	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		lmi_ack	: OUT STD_LOGIC;
		lmi_dout	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		npd_alloc_1cred_vc0	: OUT STD_LOGIC;
		npd_cred_vio_vc0	: OUT STD_LOGIC;
		nph_alloc_1cred_vc0	: OUT STD_LOGIC;
		nph_cred_vio_vc0	: OUT STD_LOGIC;
		pme_to_sr	: OUT STD_LOGIC;
		r2c_err0	: OUT STD_LOGIC;
		rate_ext	: OUT STD_LOGIC;
		rc_gxb_powerdown	: OUT STD_LOGIC;
		rc_rx_analogreset	: OUT STD_LOGIC;
		rc_rx_digitalreset	: OUT STD_LOGIC;
		rc_tx_digitalreset	: OUT STD_LOGIC;
		reset_status	: OUT STD_LOGIC;
		rx_fifo_empty0	: OUT STD_LOGIC;
		rx_fifo_full0	: OUT STD_LOGIC;
		rx_st_bardec0	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_be0	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_be0_p1	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_data0	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		rx_st_data0_p1	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		rx_st_eop0	: OUT STD_LOGIC;
		rx_st_eop0_p1	: OUT STD_LOGIC;
		rx_st_err0	: OUT STD_LOGIC;
		rx_st_sop0	: OUT STD_LOGIC;
		rx_st_sop0_p1	: OUT STD_LOGIC;
		rx_st_valid0	: OUT STD_LOGIC;
		serr_out	: OUT STD_LOGIC;
		suc_spd_neg	: OUT STD_LOGIC;
		swdn_wake	: OUT STD_LOGIC;
		swup_hotrst	: OUT STD_LOGIC;
		test_out	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		tl_cfg_add	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		tl_cfg_ctl	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		tl_cfg_ctl_wr	: OUT STD_LOGIC;
		tl_cfg_sts	: OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
		tl_cfg_sts_wr	: OUT STD_LOGIC;
		tlbp_dl_ack_phypm	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		tlbp_dl_ack_requpfc	: OUT STD_LOGIC;
		tlbp_dl_ack_sndupfc	: OUT STD_LOGIC;
		tlbp_dl_current_deemp	: OUT STD_LOGIC;
		tlbp_dl_currentspeed	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		tlbp_dl_dll_req	: OUT STD_LOGIC;
		tlbp_dl_err_dll	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
		tlbp_dl_errphy	: OUT STD_LOGIC;
		tlbp_dl_link_autobdw_status	: OUT STD_LOGIC;
		tlbp_dl_link_bdwmng_status	: OUT STD_LOGIC;
		tlbp_dl_rpbuf_emp	: OUT STD_LOGIC;
		tlbp_dl_rst_enter_comp_bit	: OUT STD_LOGIC;
		tlbp_dl_rst_tx_margin_field	: OUT STD_LOGIC;
		tlbp_dl_rx_typ_pm	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
		tlbp_dl_rx_valpm	: OUT STD_LOGIC;
		tlbp_dl_tx_ackpm	: OUT STD_LOGIC;
		tlbp_dl_up	: OUT STD_LOGIC;
		tlbp_dl_vc_status	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		tlbp_link_up	: OUT STD_LOGIC;
		tx_cred0	: OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
		tx_deemph	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		tx_fifo_empty0	: OUT STD_LOGIC;
		tx_fifo_full0	: OUT STD_LOGIC;
		tx_fifo_rdptr0	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		tx_fifo_wrptr0	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		tx_margin	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
		tx_st_ready0	: OUT STD_LOGIC;
		use_pcie_reconfig	: OUT STD_LOGIC;
		wake_oen	: OUT STD_LOGIC;
		derr_cor_ext_rcv1	: OUT STD_LOGIC;
		npd_alloc_1cred_vc1	: OUT STD_LOGIC;
		npd_cred_vio_vc1	: OUT STD_LOGIC;
		nph_alloc_1cred_vc1	: OUT STD_LOGIC;
		nph_cred_vio_vc1	: OUT STD_LOGIC;
		r2c_err1	: OUT STD_LOGIC;
		rx_fifo_empty1	: OUT STD_LOGIC;
		rx_fifo_full1	: OUT STD_LOGIC;
		rx_st_bardec1	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_be1	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_be1_p1	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rx_st_data1	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		rx_st_data1_p1	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		rx_st_eop1	: OUT STD_LOGIC;
		rx_st_eop1_p1	: OUT STD_LOGIC;
		rx_st_err1	: OUT STD_LOGIC;
		rx_st_sop1	: OUT STD_LOGIC;
		rx_st_sop1_p1	: OUT STD_LOGIC;
		rx_st_valid1	: OUT STD_LOGIC;
		tx_cred1	: OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
		tx_fifo_empty1	: OUT STD_LOGIC;
		tx_fifo_full1	: OUT STD_LOGIC;
		tx_fifo_rdptr1	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		tx_fifo_wrptr1	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		tx_st_ready1	: OUT STD_LOGIC;
		powerdown0_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity0_ext	: OUT STD_LOGIC;
		txcompl0_ext	: OUT STD_LOGIC;
		txdata0_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak0_ext	: OUT STD_LOGIC;
		txdetectrx0_ext	: OUT STD_LOGIC;
		txelecidle0_ext	: OUT STD_LOGIC;
		powerdown1_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity1_ext	: OUT STD_LOGIC;
		txcompl1_ext	: OUT STD_LOGIC;
		txdata1_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak1_ext	: OUT STD_LOGIC;
		txdetectrx1_ext	: OUT STD_LOGIC;
		txelecidle1_ext	: OUT STD_LOGIC;
		powerdown2_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity2_ext	: OUT STD_LOGIC;
		txcompl2_ext	: OUT STD_LOGIC;
		txdata2_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak2_ext	: OUT STD_LOGIC;
		txdetectrx2_ext	: OUT STD_LOGIC;
		txelecidle2_ext	: OUT STD_LOGIC;
		powerdown3_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity3_ext	: OUT STD_LOGIC;
		txcompl3_ext	: OUT STD_LOGIC;
		txdata3_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak3_ext	: OUT STD_LOGIC;
		txdetectrx3_ext	: OUT STD_LOGIC;
		txelecidle3_ext	: OUT STD_LOGIC;
		powerdown4_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity4_ext	: OUT STD_LOGIC;
		txcompl4_ext	: OUT STD_LOGIC;
		txdata4_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak4_ext	: OUT STD_LOGIC;
		txdetectrx4_ext	: OUT STD_LOGIC;
		txelecidle4_ext	: OUT STD_LOGIC;
		powerdown5_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity5_ext	: OUT STD_LOGIC;
		txcompl5_ext	: OUT STD_LOGIC;
		txdata5_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak5_ext	: OUT STD_LOGIC;
		txdetectrx5_ext	: OUT STD_LOGIC;
		txelecidle5_ext	: OUT STD_LOGIC;
		powerdown6_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity6_ext	: OUT STD_LOGIC;
		txcompl6_ext	: OUT STD_LOGIC;
		txdata6_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak6_ext	: OUT STD_LOGIC;
		txdetectrx6_ext	: OUT STD_LOGIC;
		txelecidle6_ext	: OUT STD_LOGIC;
		powerdown7_ext	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rxpolarity7_ext	: OUT STD_LOGIC;
		txcompl7_ext	: OUT STD_LOGIC;
		txdata7_ext	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak7_ext	: OUT STD_LOGIC;
		txdetectrx7_ext	: OUT STD_LOGIC;
		txelecidle7_ext	: OUT STD_LOGIC
	);

	END COMPONENT;

BEGIN
	signal_wire0  <= (others => '0');
	signal_wire1  <=  '0';
	signal_wire2  <=  '0';
	signal_wire3  <=  '0';
	signal_wire4  <=  '0';
	signal_wire5  <=  '0';
	signal_wire6  <= (others => '0');
	signal_wire7  <= (others => '0');
	signal_wire8  <= (others => '0');
	signal_wire9  <= (others => '0');
	signal_wire10  <=  '1';
	signal_wire11  <=  '0';
	signal_wire12  <=  '0';
	signal_wire13  <= (others => '0');
	signal_wire14  <= (others => '0');
	signal_wire15  <= (others => '0');
	signal_wire16  <=  '0';
	signal_wire17  <= (others => '0');
	signal_wire18  <= (others => '0');
	signal_wire19  <= (others => '0');
	signal_wire20  <=  '0';
	signal_wire21  <=  '0';
	signal_wire22  <=  '0';
	signal_wire23  <=  '0';
	signal_wire24  <=  '0';
	signal_wire25  <= (others => '0');
	signal_wire26  <=  '0';
	signal_wire27  <= (others => '0');
	signal_wire28  <= (others => '0');
	signal_wire29  <= (others => '0');
	signal_wire30  <= (others => '0');
	signal_wire31  <=  '0';
	signal_wire32  <=  '0';
	signal_wire33  <= (others => '0');
	signal_wire34  <= (others => '0');
	signal_wire35  <=  '0';
	signal_wire36  <=  '0';
	signal_wire37  <=  '0';
	signal_wire38  <=  '0';
	signal_wire39  <=  '0';
	signal_wire40  <=  '0';
	signal_wire41  <=  '0';
	signal_wire42  <= (others => '0');
	signal_wire43  <=  '0';
	signal_wire44  <=  '0';
	signal_wire45  <= (others => '0');
	signal_wire46  <=  '0';
	signal_wire47  <=  '0';
	signal_wire48  <= (others => '0');
	signal_wire49  <=  '0';
	signal_wire50  <=  '0';
	signal_wire51  <= (others => '0');
	signal_wire52  <=  '0';
	signal_wire53  <=  '0';
	signal_wire54  <= (others => '0');
	signal_wire55  <=  '0';
	signal_wire56  <=  '0';
	signal_wire57  <= (others => '0');
	signal_wire58  <=  '0';
	signal_wire59  <=  '0';
	signal_wire60  <= (others => '0');
	signal_wire61  <=  '0';
	signal_wire62  <=  '0';
	signal_wire63  <= (others => '0');
	signal_wire64  <=  '0';
	signal_wire65  <=  '0';
	signal_wire66  <= (others => '0');
	signal_wire67  <=  '0';
	signal_wire68  <=  '0';
	signal_wire69  <= (others => '0');
	signal_wire70  <=  '0';
	signal_wire71  <=  '0';
	signal_wire72  <= (others => '0');
	signal_wire73  <=  '0';
	signal_wire74  <=  '0';
	signal_wire75  <= (others => '0');
	signal_wire76  <=  '0';
	signal_wire77  <=  '0';
	signal_wire78  <= (others => '0');
	signal_wire79  <=  '0';
	signal_wire80  <=  '0';
	signal_wire81  <= (others => '0');
	signal_wire82  <=  '0';

	altpcie_hip_pipen1b_inst : altpcie_hip_pipen1b
	GENERIC MAP (
		tx_cdc_full_value => 12,
		CB_PCIE_MODE => 0,
		CG_AVALON_S_ADDR_WIDTH => 31,
		CG_COMMON_CLOCK_MODE => 1,
		CG_IMPL_CRA_AV_SLAVE_PORT => 1,
		INTENDED_DEVICE_FAMILY => "Cyclone IV GX",
		CB_A2P_ADDR_MAP_NUM_ENTRIES => 2,
		CB_A2P_ADDR_MAP_PASS_THRU_BITS => 30,
		CB_A2P_ADDR_MAP_IS_FIXED => 0,
		CB_A2P_ADDR_MAP_FIXED_TABLE => X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000",
		CB_P2A_AVALON_ADDR_B0 => X"00000000",
		CB_P2A_AVALON_ADDR_B1 => X"00040000",
		CB_P2A_AVALON_ADDR_B2 => X"00000000",
		CB_P2A_AVALON_ADDR_B3 => X"00000000",
		CB_P2A_AVALON_ADDR_B4 => X"00000000",
		CB_P2A_AVALON_ADDR_B5 => X"00000000",
		TL_SELECTION  => 1,
		bypass_tl => "true",
		AST_LITE => 0,
		p_pcie_hip_type => "2",
		retry_buffer_last_active_address => "255",
		advanced_errors => "false",
		bar0_io_space => "false",
		bar0_64bit_mem_space => "false",
		bar0_prefetchable => "false",
		bar0_size_mask => 15,
		bar1_io_space => "false",
		bar1_64bit_mem_space => "false",
		bar1_prefetchable => "false",
		bar1_size_mask => 18,
		enable_ecrc_check => "false",
		enable_ecrc_gen => "false",
		enable_l1_aspm => "false",
		l01_entry_latency => 31,
		core_clk_source  => "pclk",
		pcie_mode => "SHARED_MODE",
		expansion_base_address_register => 0,
		extend_tag_field => "false",
		bypass_cdc => "false",
		vc_arbitration => 0,
		no_soft_reset => "false",
		enable_ch0_pclk_out => "true",
		core_clk_divider => 4,
		millisecond_cycle_count => 125000,
		single_rx_detect => 1,
		enable_coreclk_out_half_rate => "false",
		enable_gen2_core => "false",
		gen2_lane_rate_mode => "false",
		lane_mask => B"11111110",
		max_link_width => 1,
		vendor_id => 6997,
		device_id => 6390,
		revision_id => 2,
		class_code => 294912,
		subsystem_vendor_id => 6997,
		subsystem_device_id => 6390,
		port_link_number => 1,
		vc_enable => B"0000000",
		vc1_clk_enable => "false",
		low_priority_vc => 0,
		max_payload_size => 1,
		msi_function_count => 0,
		endpoint_l0_latency => 0,
		endpoint_l1_latency => 0,
		diffclock_nfts_count => 255,
		sameclock_nfts_count => 255,
		l1_exit_latency_sameclock => 7,
		l1_exit_latency_diffclock => 7,
		l0_exit_latency_sameclock => 7,
		l0_exit_latency_diffclock => 7,
		enable_msi_64bit_addressing => "true",
		gen2_diffclock_nfts_count => 255,
		gen2_sameclock_nfts_count => 255,
		enable_function_msix_support => "false",
		credit_buffer_allocation_aux => "ABSOLUTE",
		eie_before_nfts_count => 4,
		enable_completion_timeout_disable => "false",
		completion_timeout => "NONE",
		enable_adapter_half_rate_mode => "false",
		msix_pba_bir => 0,
		msix_pba_offset => 0,
		msix_table_bir => 0,
		msix_table_offset => 0,
		msix_table_size => 0,
		use_crc_forwarding => "false",
		surprise_down_error_support => "false",
		dll_active_report_support => "false",
		bar_io_window_size => "32BIT",
		bar_prefetchable => 32,
		hot_plug_support => B"0000000",
		no_command_completed => "true",
		slot_power_limit => 0,
		slot_power_scale => 0,
		slot_number => 0,
		enable_slot_register => "false",
		vc0_rx_flow_ctrl_posted_header => 28,
		vc0_rx_flow_ctrl_posted_data => 198,
		vc0_rx_flow_ctrl_nonposted_header => 30,
		vc0_rx_flow_ctrl_nonposted_data => 0,
		vc0_rx_flow_ctrl_compl_header => 0,
		vc0_rx_flow_ctrl_compl_data => 0,
		RX_BUF => 10,
		RH_NUM => 7,
		G_TAG_NUM0  => 32
	)
	PORT MAP (
		AvlClk_i  =>  AvlClk_i,
		CraAddress_i  =>  CraAddress_i,
		CraByteEnable_i  =>  CraByteEnable_i,
		CraChipSelect_i  =>  CraChipSelect_i,
		CraRead  =>  CraRead,
		CraWrite  =>  CraWrite,
		CraWriteData_i  =>  CraWriteData_i,
		Rstn_i  =>  Rstn_i,
		RxmIrqNum_i  =>  RxmIrqNum_i,
		RxmIrq_i  =>  RxmIrq_i,
		RxmReadDataValid_i  =>  RxmReadDataValid_i,
		RxmReadData_i  =>  RxmReadData_i,
		RxmWaitRequest_i  =>  RxmWaitRequest_i,
		TxsAddress_i  =>  TxsAddress_i,
		TxsBurstCount_i  =>  TxsBurstCount_i,
		TxsByteEnable_i  =>  TxsByteEnable_i,
		TxsChipSelect_i  =>  TxsChipSelect_i,
		TxsRead_i  =>  TxsRead_i,
		TxsWriteData_i  =>  TxsWriteData_i,
		TxsWrite_i  =>  TxsWrite_i,
		aer_msi_num  =>  aer_msi_num,
		app_int_sts  =>  app_int_sts,
		app_msi_num  =>  app_msi_num,
		app_msi_req  =>  app_msi_req,
		app_msi_tc  =>  app_msi_tc,
		avs_pcie_reconfig_address  =>  signal_wire0,
		avs_pcie_reconfig_chipselect  =>  signal_wire1,
		avs_pcie_reconfig_clk  =>  signal_wire2,
		avs_pcie_reconfig_read  =>  signal_wire3,
		avs_pcie_reconfig_rstn  =>  signal_wire4,
		avs_pcie_reconfig_write  =>  signal_wire5,
		avs_pcie_reconfig_writedata  =>  signal_wire6,
		core_clk_in  =>  core_clk_in,
		cpl_err  =>  cpl_err,
		cpl_pending  =>  cpl_pending,
		crst  =>  crst,
		hpg_ctrler  =>  hpg_ctrler,
		lmi_addr  =>  lmi_addr,
		lmi_din  =>  lmi_din,
		lmi_rden  =>  lmi_rden,
		lmi_wren  =>  lmi_wren,
		mode  =>  signal_wire7,
		npor  =>  npor,
		pclk_central  =>  pclk_central,
		pclk_ch0  =>  pclk_ch0,
		pex_msi_num  =>  pex_msi_num,
		pld_clk  =>  pld_clk,
		pll_fixed_clk  =>  pll_fixed_clk,
		pm_auxpwr  =>  pm_auxpwr,
		pm_data  =>  pm_data,
		pm_event  =>  pm_event,
		pme_to_cr  =>  pme_to_cr,
		rc_areset  =>  rc_areset,
		rc_inclk_eq_125mhz  =>  rc_inclk_eq_125mhz,
		rc_pll_locked  =>  rc_pll_locked,
		rc_rx_pll_locked_one  =>  rc_rx_pll_locked_one,
		rx_st_mask0  =>  rx_st_mask0,
		rx_st_ready0  =>  rx_st_ready0,
		srst  =>  srst,
		swdn_in  =>  signal_wire8,
		swup_in  =>  signal_wire9,
		test_in  =>  test_in,
		tl_slotclk_cfg  =>  signal_wire10,
		tlbp_dl_aspm_cr0  =>  signal_wire11,
		tlbp_dl_comclk_reg  =>  signal_wire12,
		tlbp_dl_ctrl_link2  =>  signal_wire13,
		tlbp_dl_data_upfc  =>  signal_wire14,
		tlbp_dl_hdr_upfc  =>  signal_wire15,
		tlbp_dl_inh_dllp  =>  signal_wire16,
		tlbp_dl_maxpload_dcr  =>  signal_wire17,
		tlbp_dl_req_phycfg  =>  signal_wire18,
		tlbp_dl_req_phypm  =>  signal_wire19,
		tlbp_dl_req_upfc  =>  signal_wire20,
		tlbp_dl_req_wake  =>  signal_wire21,
		tlbp_dl_rx_ecrcchk  =>  signal_wire22,
		tlbp_dl_snd_upfc  =>  signal_wire23,
		tlbp_dl_tx_reqpm  =>  signal_wire24,
		tlbp_dl_tx_typpm  =>  signal_wire25,
		tlbp_dl_txcfg_extsy  =>  signal_wire26,
		tlbp_dl_typ_upfc  =>  signal_wire27,
		tlbp_dl_vc_ctrl  =>  signal_wire28,
		tlbp_dl_vcid_map  =>  signal_wire29,
		tlbp_dl_vcid_upfc  =>  signal_wire30,
		tx_st_data0  =>  tx_st_data0,
		tx_st_data0_p1  =>  tx_st_data0_p1,
		tx_st_eop0  =>  tx_st_eop0,
		tx_st_eop0_p1  =>  tx_st_eop0_p1,
		tx_st_err0  =>  tx_st_err0,
		tx_st_sop0  =>  tx_st_sop0,
		tx_st_sop0_p1  =>  tx_st_sop0_p1,
		tx_st_valid0  =>  tx_st_valid0,
		rx_st_mask1  =>  signal_wire31,
		rx_st_ready1  =>  signal_wire32,
		tx_st_data1  =>  signal_wire33,
		tx_st_data1_p1  =>  signal_wire34,
		tx_st_eop1  =>  signal_wire35,
		tx_st_eop1_p1  =>  signal_wire36,
		tx_st_err1  =>  signal_wire37,
		tx_st_sop1  =>  signal_wire38,
		tx_st_sop1_p1  =>  signal_wire39,
		tx_st_valid1  =>  signal_wire40,
		phystatus0_ext  =>  phystatus0_ext,
		rxdata0_ext  =>  rxdata0_ext,
		rxdatak0_ext  =>  rxdatak0_ext,
		rxelecidle0_ext  =>  rxelecidle0_ext,
		rxstatus0_ext  =>  rxstatus0_ext,
		rxvalid0_ext  =>  rxvalid0_ext,
		phystatus1_ext  =>  signal_wire41,
		rxdata1_ext  =>  signal_wire42,
		rxdatak1_ext  =>  signal_wire43,
		rxelecidle1_ext  =>  signal_wire44,
		rxstatus1_ext  =>  signal_wire45,
		rxvalid1_ext  =>  signal_wire46,
		phystatus2_ext  =>  signal_wire47,
		rxdata2_ext  =>  signal_wire48,
		rxdatak2_ext  =>  signal_wire49,
		rxelecidle2_ext  =>  signal_wire50,
		rxstatus2_ext  =>  signal_wire51,
		rxvalid2_ext  =>  signal_wire52,
		phystatus3_ext  =>  signal_wire53,
		rxdata3_ext  =>  signal_wire54,
		rxdatak3_ext  =>  signal_wire55,
		rxelecidle3_ext  =>  signal_wire56,
		rxstatus3_ext  =>  signal_wire57,
		rxvalid3_ext  =>  signal_wire58,
		phystatus4_ext  =>  signal_wire59,
		rxdata4_ext  =>  signal_wire60,
		rxdatak4_ext  =>  signal_wire61,
		rxelecidle4_ext  =>  signal_wire62,
		rxstatus4_ext  =>  signal_wire63,
		rxvalid4_ext  =>  signal_wire64,
		phystatus5_ext  =>  signal_wire65,
		rxdata5_ext  =>  signal_wire66,
		rxdatak5_ext  =>  signal_wire67,
		rxelecidle5_ext  =>  signal_wire68,
		rxstatus5_ext  =>  signal_wire69,
		rxvalid5_ext  =>  signal_wire70,
		phystatus6_ext  =>  signal_wire71,
		rxdata6_ext  =>  signal_wire72,
		rxdatak6_ext  =>  signal_wire73,
		rxelecidle6_ext  =>  signal_wire74,
		rxstatus6_ext  =>  signal_wire75,
		rxvalid6_ext  =>  signal_wire76,
		phystatus7_ext  =>  signal_wire77,
		rxdata7_ext  =>  signal_wire78,
		rxdatak7_ext  =>  signal_wire79,
		rxelecidle7_ext  =>  signal_wire80,
		rxstatus7_ext  =>  signal_wire81,
		rxvalid7_ext  =>  signal_wire82,
		CraIrq_o  =>  CraIrq_o,
		CraReadData_o  =>  CraReadData_o,
		CraWaitRequest_o  =>  CraWaitRequest_o,
		RxmAddress_o  =>  RxmAddress_o,
		RxmBurstCount_o  =>  RxmBurstCount_o,
		RxmByteEnable_o  =>  RxmByteEnable_o,
		RxmRead_o  =>  RxmRead_o,
		RxmWriteData_o  =>  RxmWriteData_o,
		RxmWrite_o  =>  RxmWrite_o,
		TxsReadDataValid_o  =>  TxsReadDataValid_o,
		TxsReadData_o  =>  TxsReadData_o,
		TxsWaitRequest_o  =>  TxsWaitRequest_o,
		app_int_ack  =>  app_int_ack,
		app_msi_ack  =>  app_msi_ack,
		avs_pcie_reconfig_readdata  =>  avs_pcie_reconfig_readdata,
		avs_pcie_reconfig_readdatavalid  =>  avs_pcie_reconfig_readdatavalid,
		avs_pcie_reconfig_waitrequest  =>  avs_pcie_reconfig_waitrequest,
		core_clk_out  =>  core_clk_out,
		derr_cor_ext_rcv0  =>  derr_cor_ext_rcv0,
		derr_cor_ext_rpl  =>  derr_cor_ext_rpl,
		derr_rpl  =>  derr_rpl,
		dl_ltssm  =>  dl_ltssm,
		dlup_exit  =>  dlup_exit,
		eidle_infer_sel  =>  eidle_infer_sel,
		ev_128ns  =>  ev_128ns,
		ev_1us  =>  ev_1us,
		hip_extraclkout  =>  hip_extraclkout,
		hotrst_exit  =>  hotrst_exit,
		int_status  =>  int_status,
		l2_exit  =>  l2_exit,
		lane_act  =>  lane_act,
		lmi_ack  =>  lmi_ack,
		lmi_dout  =>  lmi_dout,
		npd_alloc_1cred_vc0  =>  npd_alloc_1cred_vc0,
		npd_cred_vio_vc0  =>  npd_cred_vio_vc0,
		nph_alloc_1cred_vc0  =>  nph_alloc_1cred_vc0,
		nph_cred_vio_vc0  =>  nph_cred_vio_vc0,
		pme_to_sr  =>  pme_to_sr,
		r2c_err0  =>  r2c_err0,
		rate_ext  =>  rate_ext,
		rc_gxb_powerdown  =>  rc_gxb_powerdown,
		rc_rx_analogreset  =>  rc_rx_analogreset,
		rc_rx_digitalreset  =>  rc_rx_digitalreset,
		rc_tx_digitalreset  =>  rc_tx_digitalreset,
		reset_status  =>  reset_status,
		rx_fifo_empty0  =>  rx_fifo_empty0,
		rx_fifo_full0  =>  rx_fifo_full0,
		rx_st_bardec0  =>  rx_st_bardec0,
		rx_st_be0  =>  rx_st_be0,
		rx_st_be0_p1  =>  rx_st_be0_p1,
		rx_st_data0  =>  rx_st_data0,
		rx_st_data0_p1  =>  rx_st_data0_p1,
		rx_st_eop0  =>  rx_st_eop0,
		rx_st_eop0_p1  =>  rx_st_eop0_p1,
		rx_st_err0  =>  rx_st_err0,
		rx_st_sop0  =>  rx_st_sop0,
		rx_st_sop0_p1  =>  rx_st_sop0_p1,
		rx_st_valid0  =>  rx_st_valid0,
		serr_out  =>  serr_out,
		suc_spd_neg  =>  suc_spd_neg,
		swdn_wake  =>  swdn_wake,
		swup_hotrst  =>  swup_hotrst,
		test_out  =>  test_out,
		tl_cfg_add  =>  tl_cfg_add,
		tl_cfg_ctl  =>  tl_cfg_ctl,
		tl_cfg_ctl_wr  =>  tl_cfg_ctl_wr,
		tl_cfg_sts  =>  tl_cfg_sts,
		tl_cfg_sts_wr  =>  tl_cfg_sts_wr,
		tlbp_dl_ack_phypm  =>  open,
		tlbp_dl_ack_requpfc  =>  open,
		tlbp_dl_ack_sndupfc  =>  open,
		tlbp_dl_current_deemp  =>  open,
		tlbp_dl_currentspeed  =>  open,
		tlbp_dl_dll_req  =>  open,
		tlbp_dl_err_dll  =>  open,
		tlbp_dl_errphy  =>  open,
		tlbp_dl_link_autobdw_status  =>  open,
		tlbp_dl_link_bdwmng_status  =>  open,
		tlbp_dl_rpbuf_emp  =>  open,
		tlbp_dl_rst_enter_comp_bit  =>  open,
		tlbp_dl_rst_tx_margin_field  =>  open,
		tlbp_dl_rx_typ_pm  =>  open,
		tlbp_dl_rx_valpm  =>  open,
		tlbp_dl_tx_ackpm  =>  open,
		tlbp_dl_up  =>  open,
		tlbp_dl_vc_status  =>  open,
		tlbp_link_up  =>  open,
		tx_cred0  =>  tx_cred0,
		tx_deemph  =>  tx_deemph,
		tx_fifo_empty0  =>  tx_fifo_empty0,
		tx_fifo_full0  =>  tx_fifo_full0,
		tx_fifo_rdptr0  =>  tx_fifo_rdptr0,
		tx_fifo_wrptr0  =>  tx_fifo_wrptr0,
		tx_margin  =>  tx_margin,
		tx_st_ready0  =>  tx_st_ready0,
		use_pcie_reconfig  =>  use_pcie_reconfig,
		wake_oen  =>  wake_oen,
		derr_cor_ext_rcv1  =>  open,
		npd_alloc_1cred_vc1  =>  open,
		npd_cred_vio_vc1  =>  open,
		nph_alloc_1cred_vc1  =>  open,
		nph_cred_vio_vc1  =>  open,
		r2c_err1  =>  open,
		rx_fifo_empty1  =>  open,
		rx_fifo_full1  =>  open,
		rx_st_bardec1  =>  open,
		rx_st_be1  =>  open,
		rx_st_be1_p1  =>  open,
		rx_st_data1  =>  open,
		rx_st_data1_p1  =>  open,
		rx_st_eop1  =>  open,
		rx_st_eop1_p1  =>  open,
		rx_st_err1  =>  open,
		rx_st_sop1  =>  open,
		rx_st_sop1_p1  =>  open,
		rx_st_valid1  =>  open,
		tx_cred1  =>  open,
		tx_fifo_empty1  =>  open,
		tx_fifo_full1  =>  open,
		tx_fifo_rdptr1  =>  open,
		tx_fifo_wrptr1  =>  open,
		tx_st_ready1  =>  open,
		powerdown0_ext  =>  powerdown0_ext,
		rxpolarity0_ext  =>  rxpolarity0_ext,
		txcompl0_ext  =>  txcompl0_ext,
		txdata0_ext  =>  txdata0_ext,
		txdatak0_ext  =>  txdatak0_ext,
		txdetectrx0_ext  =>  txdetectrx0_ext,
		txelecidle0_ext  =>  txelecidle0_ext,
		powerdown1_ext  =>  open,
		rxpolarity1_ext  =>  open,
		txcompl1_ext  =>  open,
		txdata1_ext  =>  open,
		txdatak1_ext  =>  open,
		txdetectrx1_ext  =>  open,
		txelecidle1_ext  =>  open,
		powerdown2_ext  =>  open,
		rxpolarity2_ext  =>  open,
		txcompl2_ext  =>  open,
		txdata2_ext  =>  open,
		txdatak2_ext  =>  open,
		txdetectrx2_ext  =>  open,
		txelecidle2_ext  =>  open,
		powerdown3_ext  =>  open,
		rxpolarity3_ext  =>  open,
		txcompl3_ext  =>  open,
		txdata3_ext  =>  open,
		txdatak3_ext  =>  open,
		txdetectrx3_ext  =>  open,
		txelecidle3_ext  =>  open,
		powerdown4_ext  =>  open,
		rxpolarity4_ext  =>  open,
		txcompl4_ext  =>  open,
		txdata4_ext  =>  open,
		txdatak4_ext  =>  open,
		txdetectrx4_ext  =>  open,
		txelecidle4_ext  =>  open,
		powerdown5_ext  =>  open,
		rxpolarity5_ext  =>  open,
		txcompl5_ext  =>  open,
		txdata5_ext  =>  open,
		txdatak5_ext  =>  open,
		txdetectrx5_ext  =>  open,
		txelecidle5_ext  =>  open,
		powerdown6_ext  =>  open,
		rxpolarity6_ext  =>  open,
		txcompl6_ext  =>  open,
		txdata6_ext  =>  open,
		txdatak6_ext  =>  open,
		txdetectrx6_ext  =>  open,
		txelecidle6_ext  =>  open,
		powerdown7_ext  =>  open,
		rxpolarity7_ext  =>  open,
		txcompl7_ext  =>  open,
		txdata7_ext  =>  open,
		txdatak7_ext  =>  open,
		txdetectrx7_ext  =>  open,
		txelecidle7_ext  =>  open
	);


END SYN;