Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Arm64 irq1 #13520

Open
wants to merge 5 commits into
base: master
Choose a base branch
from
Open

Arm64 irq1 #13520

wants to merge 5 commits into from
+798 −936

Conversation

lipengfei28
Copy link
Contributor

Summary

arm64: simply the vectors

Impact

Testing

@lipengfei28
Copy link
Contributor Author 

1. save FPU regs enter exception and retore exit exception every time
2. simp the vectors
3. save sp_el0 enter exception and restore sp_el0 exit exception every time

@lipengfei28 lipengfei28 force-pushed the arm64_irq1 branch 4 times, most recently from 1e1c326 to 2b07421 Compare September 18, 2024 07:04
xiaoxiang781216
xiaoxiang781216 reviewed Sep 18, 2024
View reviewed changes
arch/arm64/src/common/arm64_syscall.c Outdated Show resolved Hide resolved
arch/arm64/src/common/arm64_syscall.c Outdated Show resolved Hide resolved
@lipengfei28 lipengfei28 force-pushed the arm64_irq1 branch 2 times, most recently from 05dae0b to 2539ba1 Compare September 19, 2024 06:45
qinwei2004 and others added 5 commits September 20, 2024 10:02
@qinwei2004 @lipengfei28
arm64: refine the fatal handler
444420e 
Summary
  The original implement for exception handler is very simple and
haven't framework for breakpoint/watchpoint routine or brk instruction.
  I refine the fatal handler and add framework for debug handler to
register or unregister. this is a prepare for watchpoint/breakpoint
implement

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
@GUIDINGLI @lipengfei28
arm64: save FPU regs every time
6759fc1 
Signed-off-by: ligd <liguiding1@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
@qinwei2004 @lipengfei28
arm64: add arm64_current_el to obtain current EL
0cf6cb7 
Summary
  Add a macro to obtain current execute level

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
@GUIDINGLI @lipengfei28
arm64: simply the vectors
8b8ab2d 
Signed-off-by: ligd <liguiding1@xiaomi.com>
@lipengfei28
Kernel build: enter exception save sp_sl0,exit exception restroe sp_el0
5d4b00a 
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
@github-actions github-actions bot added the Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. label Sep 20, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@xiaoxiang781216 xiaoxiang781216 xiaoxiang781216 left review comments

@acassis acassis acassis approved these changes

Assignees
No one assigned
Labels
Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
5 participants
@lipengfei28 @acassis @xiaoxiang781216 @qinwei2004 @GUIDINGLI