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Remove PDCM from the sapphirerapids list #119

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merged 1 commit into from
Oct 14, 2024

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linsword13
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PDCM is not a feature currently used by compilers, see for instance https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html.

For GCP VMs, only ones that have vPMU enabled would have PDCM exposed in the guest. Including PDCM would therefore cause these non-vPMU-enabled VMs to be identified as icelake instead.

`PDCM` is not a feature currently used by compilers, see for instance
https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html.

For GCP VMs, only ones that have vPMU [enabled](https://cloud.google.com/compute/docs/manage-pmu-in-vms) would have `PDCM` exposed in the guest. Including `PDCM` would therefore cause these non-vPMU-enabled VMs to be identified as icelake instead.
@alalazo alalazo self-assigned this Sep 16, 2024
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@alalazo, wonder if you have feedback on this PR? Thanks!

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From GCC man pages

Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,
               CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2 VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB, MOVDIRI, MOVDIR64B,
               AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI and AVX512BF16 instruction set support.

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alalazo commented Oct 14, 2024

@linsword13 Thanks!

@alalazo alalazo merged commit 0c7bd58 into archspec:master Oct 14, 2024
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2 participants