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limit the number of VM regs to 16 (RV32e) #304

Merged
merged 2 commits into from
Jan 8, 2025
Merged

limit the number of VM regs to 16 (RV32e) #304

merged 2 commits into from
Jan 8, 2025

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poszu
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@poszu poszu commented Jan 7, 2025

Part of #18.

Removed registers X16+ from the VM and changed how they are represented in the VM from memory-mapped at "addresses" 0-15 to a separate structure that is also responsible for keeping invariants like the X0 always zero.

Note that, in many places in the VM, a raw u32 taken from Instruction is converted to a Register, which may panic if the value is > 15. In the following PR, I will change disassembling logic to convert raw integers to Register enum variants at disassembly time to prevent panics at the guest program execution time.

@poszu poszu force-pushed the limit-vm-registers branch from 878d990 to 4533ff4 Compare January 7, 2025 16:23
@poszu poszu requested a review from jellonek January 8, 2025 07:56
@poszu poszu marked this pull request as ready for review January 8, 2025 07:56
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jellonek commented Jan 8, 2025

Note: that is partially invalidating the info which is still in README.md about:

Athena includes a virtual machine (VM) based on the RISC-V ISA, including support for RV32IM and RV32EM,

@poszu poszu enabled auto-merge January 8, 2025 09:05
@poszu poszu added this pull request to the merge queue Jan 8, 2025
Merged via the queue into main with commit 290842d Jan 8, 2025
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2 participants