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Fix wio_terminal
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Adrian Geipert committed May 14, 2023
1 parent a5103a5 commit a78c73d
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Showing 3 changed files with 5 additions and 5 deletions.
2 changes: 1 addition & 1 deletion boards/wio_terminal/src/sensors.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use atsamd_hal::adc::Adc;
use atsamd_hal::clock::GenericClockController;
use atsamd_hal::pac::gclk::pchctrl::GEN_A::GCLK11;
use atsamd_hal::pac::gclk::pchctrl::GENSELECT_A::GCLK11;
use atsamd_hal::pac::{ADC1, MCLK, SERCOM4};
use atsamd_hal::sercom::{i2c, IoSet3, Sercom4};
use atsamd_hal::time::U32Ext;
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6 changes: 3 additions & 3 deletions boards/wio_terminal/src/serial.rs
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ use atsamd_hal::time::Hertz;
#[cfg(feature = "usb")]
use atsamd_hal::usb::{usb_device::bus::UsbBusAllocator, UsbBus};
#[cfg(feature = "usb")]
use pac::gclk::{genctrl::SRC_A, pchctrl::GEN_A};
use pac::gclk::{genctrl::SRCSELECT_A, pchctrl::GENSELECT_A};

use super::pins::aliases::*;

Expand Down Expand Up @@ -69,8 +69,8 @@ impl Usb {
clocks: &mut GenericClockController,
mclk: &mut MCLK,
) -> UsbBusAllocator<UsbBus> {
clocks.configure_gclk_divider_and_source(GEN_A::GCLK2, 1, SRC_A::DFLL, false);
let usb_gclk = clocks.get_gclk(GEN_A::GCLK2).unwrap();
clocks.configure_gclk_divider_and_source(GENSELECT_A::GCLK2, 1, SRCSELECT_A::DFLL, false);
let usb_gclk = clocks.get_gclk(GENSELECT_A::GCLK2).unwrap();
let usb_clock = &clocks.usb(&usb_gclk).unwrap();

UsbBusAllocator::new(UsbBus::new(usb_clock, mclk, self.dm, self.dp, usb))
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2 changes: 1 addition & 1 deletion boards/wio_terminal/src/sound.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use atsamd_hal::adc::Adc;
use atsamd_hal::clock::GenericClockController;
use atsamd_hal::pac::gclk::pchctrl::GEN_A::GCLK11;
use atsamd_hal::pac::gclk::pchctrl::GENSELECT_A::GCLK11;
use atsamd_hal::pac::{ADC1, MCLK, TCC0};
use atsamd_hal::pwm::{TCC0Pinout, Tcc0Pwm};
use atsamd_hal::time::U32Ext;
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