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Update PAC's to svd2rust 0.30.2 #683

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merged 29 commits into from
Oct 26, 2023
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8723087
Update svd2rust and form version
May 7, 2023
c53b3d7
CreatePatch file for the EVSYS channel
May 8, 2023
054e4fe
Regenerate PAC's with svd2rut 0.28.0
May 7, 2023
abfa485
Apply manual patch for wrong generation of svd2rust
May 14, 2023
918eea5
Update Cargo.toml to the new Versions of the pacs
May 13, 2023
7be5e8e
Update hal to the new pacs
May 13, 2023
7f02579
Create new optional dependency for critical sections
May 13, 2023
9d20393
Make the tier one examples compileable
May 14, 2023
d078c06
Update the changelog
May 14, 2023
a5103a5
Fix formating
May 14, 2023
59df225
Fix wio_terminal
May 14, 2023
328d713
Rename port config variables back to the right name
May 14, 2023
9f1f658
Add critical section to crates.json
May 15, 2023
91a2f19
Change the rename in EVSYS to the Channel struct.
May 17, 2023
85feef0
Merge atsamd-rs/master
jbeaurivage Oct 24, 2023
b11b060
Update to svd2rust 0.30.2
jbeaurivage Oct 24, 2023
3833523
Update changelogs
jbeaurivage Oct 24, 2023
74d6848
Make critical-section a default feature and update changelog
jbeaurivage Oct 24, 2023
7666fce
Turn on critical-section-single-core cortex-m flag in PACs
jbeaurivage Oct 24, 2023
43931de
Remove feature-gating of critical-section in PACs and update changelogs
jbeaurivage Oct 24, 2023
54651e7
Add changelog entries for Tier 1 boards
jbeaurivage Oct 24, 2023
06c5dae
Merge branch 'master' into tremoneck_updatePAC
jbeaurivage Oct 25, 2023
2803d11
Remove critical-section features from crates.json
jbeaurivage Oct 25, 2023
1be89f3
Remove critical-section features of T1 BSPs
jbeaurivage Oct 25, 2023
932f2e9
Merge pull request #2 from jbeaurivage/tremoneck_updatePAC
Tremoneck Oct 25, 2023
2b8d954
Remove "critical-section" feature of PAC libs
jbeaurivage Oct 26, 2023
3c51912
Fix wio_terminal build
jbeaurivage Oct 26, 2023
094fd0a
wio_terminal is not a Tier 1 board
jbeaurivage Oct 26, 2023
8a199c2
Merge pull request #3 from jbeaurivage/tremoneck_updatePAC
Tremoneck Oct 26, 2023
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2 changes: 2 additions & 0 deletions boards/atsame54_xpro/CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
# Unreleased

- Update the PACs to svd2rust 0.30.2.

# v0.6.0
- Limit RAM memory to avoid HardFaults when `UROW:ECCRAM` is enabled
- Remove re-export of `cortex-m-rt::entry`
Expand Down
4 changes: 4 additions & 0 deletions boards/atsame54_xpro/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,10 @@ readme = "README.md"
version = "0.7"
optional = true

[dependencies.cortex-m]
version = "0.7"
features = ["critical-section-single-core"]

[dependencies.atsamd-hal]
path = "../../hal"
version = "0.16.0"
Expand Down
6 changes: 3 additions & 3 deletions boards/atsame54_xpro/src/devices.rs
Original file line number Diff line number Diff line change
Expand Up @@ -367,10 +367,10 @@ pub fn usb_allocator(
dm: impl Into<UsbDm>,
dp: impl Into<UsbDp>,
) -> UsbBusAllocator<UsbBus> {
use pac::gclk::{genctrl::SRC_A, pchctrl::GEN_A};
use pac::gclk::{genctrl::SRCSELECT_A, pchctrl::GENSELECT_A};

clocks.configure_gclk_divider_and_source(GEN_A::GCLK2, 1, SRC_A::DFLL, false);
let usb_gclk = clocks.get_gclk(GEN_A::GCLK2).unwrap();
clocks.configure_gclk_divider_and_source(GENSELECT_A::GCLK2, 1, SRCSELECT_A::DFLL, false);
let usb_gclk = clocks.get_gclk(GENSELECT_A::GCLK2).unwrap();
let usb_clock = &clocks.usb(&usb_gclk).unwrap();
let (dm, dp) = (dm.into(), dp.into());
UsbBusAllocator::new(UsbBus::new(usb_clock, mclk, dm, dp, usb))
Expand Down
2 changes: 2 additions & 0 deletions boards/feather_m0/CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
# Unreleased

- Update the PACs to svd2rust 0.30.2.

# v0.13.0

- Replace homebrew time library with `fugit` (#672)
Expand Down
4 changes: 4 additions & 0 deletions boards/feather_m0/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,10 @@ path = "../../hal"
version = "0.16.0"
default-features = false

[dependencies.cortex-m]
version = "0.7"
features = ["critical-section-single-core"]

[dependencies.usb-device]
version = "0.2"
optional = true
Expand Down
2 changes: 2 additions & 0 deletions boards/feather_m4/CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
# Unreleased

- Update the PACs to svd2rust 0.30.2.

# v0.11.0

- Replace homebrew time library with `fugit` (#672)
Expand Down
5 changes: 4 additions & 1 deletion boards/feather_m4/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,10 @@ chip = "ATSAMD51J19A"
version = "0.7"
optional = true

[dependencies.cortex-m]
version = "0.7"
features = ["critical-section-single-core"]

[dependencies.atsamd-hal]
path = "../../hal"
version = "0.16.0"
Expand All @@ -29,7 +33,6 @@ version = "0.2"
optional = true

[dev-dependencies]
cortex-m = "0.7"
usbd-serial = "0.1"
cortex-m-rtic = "0.6.0-rc.2"
panic-halt = "0.2"
Expand Down
6 changes: 3 additions & 3 deletions boards/feather_m4/examples/serial.rs
Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,8 @@ use panic_semihosting as _;
use bsp::{entry, periph_alias, pin_alias};
use hal::clock::GenericClockController;
use hal::delay::Delay;
use hal::pac::gclk::genctrl::SRC_A;
use hal::pac::gclk::pchctrl::GEN_A;
use hal::pac::gclk::genctrl::SRCSELECT_A;
use hal::pac::gclk::pchctrl::GENSELECT_A;
use hal::pac::{CorePeripherals, Peripherals};
use hal::prelude::*;

Expand All @@ -28,7 +28,7 @@ fn main() -> ! {
&mut peripherals.OSCCTRL,
&mut peripherals.NVMCTRL,
);
clocks.configure_gclk_divider_and_source(GEN_A::GCLK2, 1, SRC_A::DFLL, false);
clocks.configure_gclk_divider_and_source(GENSELECT_A::GCLK2, 1, SRCSELECT_A::DFLL, false);

let pins = bsp::Pins::new(peripherals.PORT);
let uart_rx = pin_alias!(pins.uart_rx);
Expand Down
6 changes: 3 additions & 3 deletions boards/feather_m4/examples/uart_poll_echo.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,8 @@ use panic_semihosting as _;
use bsp::{entry, periph_alias, pin_alias};
use hal::clock::GenericClockController;
use hal::delay::Delay;
use hal::pac::gclk::genctrl::SRC_A;
use hal::pac::gclk::pchctrl::GEN_A;
use hal::pac::gclk::genctrl::SRCSELECT_A;
use hal::pac::gclk::pchctrl::GENSELECT_A;
use hal::pac::{CorePeripherals, Peripherals};
use hal::prelude::*;

Expand All @@ -35,7 +35,7 @@ fn main() -> ! {
&mut peripherals.OSCCTRL,
&mut peripherals.NVMCTRL,
);
clocks.configure_gclk_divider_and_source(GEN_A::GCLK2, 1, SRC_A::DFLL, false);
clocks.configure_gclk_divider_and_source(GENSELECT_A::GCLK2, 1, SRCSELECT_A::DFLL, false);

let pins = bsp::Pins::new(peripherals.PORT);
let mut delay = Delay::new(core.SYST, &mut clocks);
Expand Down
6 changes: 3 additions & 3 deletions boards/feather_m4/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -267,10 +267,10 @@ pub fn usb_allocator(
clocks: &mut GenericClockController,
mclk: &mut pac::MCLK,
) -> UsbBusAllocator<UsbBus> {
use pac::gclk::{genctrl::SRC_A, pchctrl::GEN_A};
use pac::gclk::{genctrl::SRCSELECT_A, pchctrl::GENSELECT_A};

clocks.configure_gclk_divider_and_source(GEN_A::GCLK2, 1, SRC_A::DFLL, false);
let usb_gclk = clocks.get_gclk(GEN_A::GCLK2).unwrap();
clocks.configure_gclk_divider_and_source(GENSELECT_A::GCLK2, 1, SRCSELECT_A::DFLL, false);
let usb_gclk = clocks.get_gclk(GENSELECT_A::GCLK2).unwrap();
let usb_clock = &clocks.usb(&usb_gclk).unwrap();
let (dm, dp) = (dm.into(), dp.into());
UsbBusAllocator::new(UsbBus::new(usb_clock, mclk, dm, dp, usb))
Expand Down
2 changes: 2 additions & 0 deletions boards/metro_m0/CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
# Unreleased

- Update the PACs to svd2rust 0.30.2.

# v0.13.0

- Replace homebrew time library with `fugit` (#672)
Expand Down
4 changes: 4 additions & 0 deletions boards/metro_m0/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,10 @@ chip = "ATSAMD21G18A"
version = "0.7"
optional = true

[dependencies.cortex-m]
version = "0.7"
features = ["critical-section-single-core"]

[dependencies.atsamd-hal]
path = "../../hal"
version = "0.16.0"
Expand Down
2 changes: 2 additions & 0 deletions boards/metro_m4/CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
# Unreleased

- Update the PACs to svd2rust 0.30.2.

# v0.12.0

- Use correct alternate for USB (#661)
Expand Down
4 changes: 4 additions & 0 deletions boards/metro_m4/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,10 @@ default-features = false
version = "0.2"
optional = true

[dependencies.cortex-m]
version = "0.7"
features = ["critical-section-single-core"]

[dev-dependencies]
cortex-m = "0.7"
usbd-serial = "0.1"
Expand Down
2 changes: 1 addition & 1 deletion boards/metro_m4/examples/adc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ use hal::adc::Adc;
use hal::clock::GenericClockController;
use hal::gpio::B;
use hal::prelude::*;
use pac::gclk::pchctrl::GEN_A::GCLK11;
use pac::gclk::pchctrl::GENSELECT_A::GCLK11;
use pac::{CorePeripherals, Peripherals};

#[entry]
Expand Down
4 changes: 2 additions & 2 deletions boards/metro_m4/examples/clock_out.rs
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@ use bsp::entry;
use hal::clock::GenericClockController;
use hal::gpio::M;

use pac::gclk::genctrl::SRC_A::DPLL0;
use pac::gclk::pchctrl::GEN_A::GCLK2;
use pac::gclk::genctrl::SRCSELECT_A::DPLL0;
use pac::gclk::pchctrl::GENSELECT_A::GCLK2;
use pac::Peripherals;

#[entry]
Expand Down
6 changes: 3 additions & 3 deletions boards/metro_m4/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -360,10 +360,10 @@ pub fn usb_allocator(
dm: impl Into<UsbDm>,
dp: impl Into<UsbDp>,
) -> UsbBusAllocator<UsbBus> {
use pac::gclk::{genctrl::SRC_A, pchctrl::GEN_A};
use pac::gclk::{genctrl::SRCSELECT_A, pchctrl::GENSELECT_A};

clocks.configure_gclk_divider_and_source(GEN_A::GCLK2, 1, SRC_A::DFLL, false);
let usb_gclk = clocks.get_gclk(GEN_A::GCLK2).unwrap();
clocks.configure_gclk_divider_and_source(GENSELECT_A::GCLK2, 1, SRCSELECT_A::DFLL, false);
let usb_gclk = clocks.get_gclk(GENSELECT_A::GCLK2).unwrap();
let usb_clock = &clocks.usb(&usb_gclk).unwrap();
let (dm, dp) = (dm.into(), dp.into());
UsbBusAllocator::new(UsbBus::new(usb_clock, mclk, dm, dp, usb))
Expand Down
2 changes: 2 additions & 0 deletions boards/samd11_bare/CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
# Unreleased

- Update the PACs to svd2rust 0.30.2.

# v0.9.0
- Update to `atsamd-hal` version `0.16.0`

Expand Down
4 changes: 4 additions & 0 deletions boards/samd11_bare/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,10 @@ chip = "ATSAMD11C14A"
version = "0.7"
optional = true

[dependencies.cortex-m]
version = "0.7"
features = ["critical-section-single-core"]

[dependencies.atsamd-hal]
path = "../../hal"
version = "0.16.0"
Expand Down
6 changes: 3 additions & 3 deletions boards/samd11_bare/examples/serial.rs
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ use panic_semihosting as _;
use hal::delay::Delay;
use hal::pac::{CorePeripherals, Peripherals};

use hal::pac::gclk::{clkctrl::GEN_A, genctrl::SRC_A};
use hal::pac::gclk::{clkctrl::GENSELECT_A, genctrl::SRCSELECT_A};
use hal::sercom::{
uart::{self, BaudMode, Oversampling},
Sercom0,
Expand All @@ -34,9 +34,9 @@ fn main() -> ! {
&mut peripherals.NVMCTRL,
);

clocks.configure_gclk_divider_and_source(GEN_A::GCLK2, 1, SRC_A::DFLL48M, false);
clocks.configure_gclk_divider_and_source(GENSELECT_A::GCLK2, 1, SRCSELECT_A::DFLL48M, false);
let gclk2 = clocks
.get_gclk(GEN_A::GCLK2)
.get_gclk(GENSELECT_A::GCLK2)
.expect("Could not get clock 2");

let pins = bsp::Pins::new(peripherals.PORT);
Expand Down
2 changes: 2 additions & 0 deletions hal/CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
# Unreleased Changes

- Update the PACs to svd2rust 0.30.2.

# v0.16.0

- Implement `Debug, Clone, Copy, Eq, PartialEq` for all HAL error types (#691).
Expand Down
34 changes: 17 additions & 17 deletions hal/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -69,27 +69,27 @@ defmt = {version = "0.3.4", optional = true}
# users should specify a corresponding variant (see below). The variant features
# will select the correct PAC, as well as other configuration features.

atsamd11c = {version = "0.12.0", path = "../pac/atsamd11c", optional = true}
atsamd11d = {version = "0.12.0", path = "../pac/atsamd11d", optional = true}
atsamd11c = {version = "0.13.0", path = "../pac/atsamd11c", optional = true}
atsamd11d = {version = "0.13.0", path = "../pac/atsamd11d", optional = true}

atsamd21e = {version = "0.12.0", path = "../pac/atsamd21e", optional = true}
atsamd21g = {version = "0.12.0", path = "../pac/atsamd21g", optional = true}
atsamd21j = {version = "0.12.0", path = "../pac/atsamd21j", optional = true}
atsamd21e = {version = "0.13.0", path = "../pac/atsamd21e", optional = true}
atsamd21g = {version = "0.13.0", path = "../pac/atsamd21g", optional = true}
atsamd21j = {version = "0.13.0", path = "../pac/atsamd21j", optional = true}

atsamd51g = {version = "0.12.0", path = "../pac/atsamd51g", optional = true}
atsamd51j = {version = "0.12.0", path = "../pac/atsamd51j", optional = true}
atsamd51n = {version = "0.12.0", path = "../pac/atsamd51n", optional = true}
atsamd51p = {version = "0.12.0", path = "../pac/atsamd51p", optional = true}
atsamd51g = {version = "0.13.0", path = "../pac/atsamd51g", optional = true}
atsamd51j = {version = "0.13.0", path = "../pac/atsamd51j", optional = true}
atsamd51n = {version = "0.13.0", path = "../pac/atsamd51n", optional = true}
atsamd51p = {version = "0.13.0", path = "../pac/atsamd51p", optional = true}

atsame51g = {version = "0.12.0", path = "../pac/atsame51g", optional = true}
atsame51j = {version = "0.12.0", path = "../pac/atsame51j", optional = true}
atsame51n = {version = "0.12.0", path = "../pac/atsame51n", optional = true}
atsame51g = {version = "0.13.0", path = "../pac/atsame51g", optional = true}
atsame51j = {version = "0.13.0", path = "../pac/atsame51j", optional = true}
atsame51n = {version = "0.13.0", path = "../pac/atsame51n", optional = true}

atsame53j = {version = "0.12.0", path = "../pac/atsame53j", optional = true}
atsame53n = {version = "0.12.0", path = "../pac/atsame53n", optional = true}
atsame53j = {version = "0.13.0", path = "../pac/atsame53j", optional = true}
atsame53n = {version = "0.13.0", path = "../pac/atsame53n", optional = true}

atsame54n = {version = "0.12.0", path = "../pac/atsame54n", optional = true}
atsame54p = {version = "0.12.0", path = "../pac/atsame54p", optional = true}
atsame54n = {version = "0.13.0", path = "../pac/atsame54n", optional = true}
atsame54p = {version = "0.13.0", path = "../pac/atsame54p", optional = true}

#===============================================================================
# Features
Expand Down Expand Up @@ -178,14 +178,14 @@ default = ["unproven"]

can = ["mcan-core"]
dma = ["unproven"]
defmt = ["dep:defmt"]
enable_unsafe_aes_newblock_cipher = []
max-channels = ["dma"]
rtic = ["rtic-monotonic"]
sdmmc = ["embedded-sdmmc"]
unproven = ["embedded-hal/unproven"]
usb = ["usb-device"]
use_rtt = ["jlink_rtt"]
defmt = ["dep:defmt"]

#===============================================================================
# Implementation-details
Expand Down
9 changes: 5 additions & 4 deletions hal/src/dmac/dma_controller.rs
Original file line number Diff line number Diff line change
Expand Up @@ -24,16 +24,17 @@ use seq_macro::seq;

#[cfg(feature = "thumbv6")]
pub use crate::pac::dmac::chctrlb::{
LVL_A as PriorityLevel, TRIGACT_A as TriggerAction, TRIGSRC_A as TriggerSource,
LVLSELECT_A as PriorityLevel, TRIGACTSELECT_A as TriggerAction,
TRIGSRCSELECT_A as TriggerSource,
};

#[cfg(feature = "thumbv7")]
pub use crate::pac::dmac::channel::{
chctrla::{
BURSTLEN_A as BurstLength, THRESHOLD_A as FifoThreshold, TRIGACT_A as TriggerAction,
TRIGSRC_A as TriggerSource,
BURSTLENSELECT_A as BurstLength, THRESHOLDSELECT_A as FifoThreshold,
TRIGACTSELECT_A as TriggerAction, TRIGSRCSELECT_A as TriggerSource,
},
chprilvl::PRILVL_A as PriorityLevel,
chprilvl::PRILVLSELECT_A as PriorityLevel,
};

use super::{
Expand Down
32 changes: 16 additions & 16 deletions hal/src/rtc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -23,14 +23,14 @@ use rtic_monotonic::Monotonic;
// SAMx5x imports
#[cfg(feature = "thumbv7")]
use crate::pac::{
rtc::mode0::ctrla::PRESCALER_A, rtc::mode0::CTRLA as MODE0_CTRLA,
rtc::mode0::ctrla::PRESCALERSELECT_A, rtc::mode0::CTRLA as MODE0_CTRLA,
rtc::mode2::CTRLA as MODE2_CTRLA, MCLK as PM,
};

// SAMD11/SAMD21 imports
#[cfg(feature = "thumbv6")]
use crate::pac::{
rtc::mode0::ctrl::PRESCALER_A, rtc::mode0::CTRL as MODE0_CTRLA,
rtc::mode0::ctrl::PRESCALERSELECT_A, rtc::mode0::CTRL as MODE0_CTRLA,
rtc::mode2::CTRL as MODE2_CTRLA, PM,
};

Expand Down Expand Up @@ -412,7 +412,7 @@ impl TimeSource for Rtc<ClockMode> {
/// Helper type for computing cycles and divider given frequency
#[derive(Debug, Clone, Copy)]
pub struct TimerParams {
pub divider: PRESCALER_A,
pub divider: PRESCALERSELECT_A,
pub cycles: u32,
}

Expand Down Expand Up @@ -440,19 +440,19 @@ impl TimerParams {
fn new_from_ticks(ticks: u32) -> Self {
let divider_value = ((ticks >> 16) + 1).next_power_of_two();
let divider = match divider_value {
1 => PRESCALER_A::DIV1,
2 => PRESCALER_A::DIV2,
4 => PRESCALER_A::DIV4,
8 => PRESCALER_A::DIV8,
16 => PRESCALER_A::DIV16,
32 => PRESCALER_A::DIV32,
64 => PRESCALER_A::DIV64,
128 => PRESCALER_A::DIV128,
256 => PRESCALER_A::DIV256,
512 => PRESCALER_A::DIV512,
1024 => PRESCALER_A::DIV1024,
_ => PRESCALER_A::DIV1024, /* would be nice to catch this at compile time
* (rust-lang/rust#51999) */
1 => PRESCALERSELECT_A::DIV1,
2 => PRESCALERSELECT_A::DIV2,
4 => PRESCALERSELECT_A::DIV4,
8 => PRESCALERSELECT_A::DIV8,
16 => PRESCALERSELECT_A::DIV16,
32 => PRESCALERSELECT_A::DIV32,
64 => PRESCALERSELECT_A::DIV64,
128 => PRESCALERSELECT_A::DIV128,
256 => PRESCALERSELECT_A::DIV256,
512 => PRESCALERSELECT_A::DIV512,
1024 => PRESCALERSELECT_A::DIV1024,
_ => PRESCALERSELECT_A::DIV1024, /* would be nice to catch this at compile time
* (rust-lang/rust#51999) */
};

let cycles: u32 = ticks / divider_value as u32;
Expand Down
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