From 8908e8cab0e02166fe34feb3a45666bcc383c1c3 Mon Sep 17 00:00:00 2001
From: Ian Rees <code@ianrees.nz>
Date: Fri, 16 Aug 2024 20:35:58 +1200
Subject: [PATCH] Wait at end of ehal 0.2 blocking SPI writes

---
 hal/CHANGELOG.md                          |  1 +
 hal/src/sercom/spi/impl_ehal_thumbv6m.rs  |  4 ++++
 hal/src/sercom/spi/impl_ehal_thumbv7em.rs | 14 ++++++++++++--
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/hal/CHANGELOG.md b/hal/CHANGELOG.md
index cbe9876a4d6..3990d28a2ff 100644
--- a/hal/CHANGELOG.md
+++ b/hal/CHANGELOG.md
@@ -1,5 +1,6 @@
 # Unreleased Changes
 
+- Fix blocking behaviour for `embedded-hal` 0.2 SPI writes
 - Fix I2C transaction to be as continuous as possible according to `embedded-hal` specification
 - Allow configuring USB clock with `GenericClockController` on atsamd11
 - fix samd51j not having i2s support
diff --git a/hal/src/sercom/spi/impl_ehal_thumbv6m.rs b/hal/src/sercom/spi/impl_ehal_thumbv6m.rs
index b212651d92c..58a9300651d 100644
--- a/hal/src/sercom/spi/impl_ehal_thumbv6m.rs
+++ b/hal/src/sercom/spi/impl_ehal_thumbv6m.rs
@@ -571,6 +571,8 @@ macro_rules! impl_blocking_spi_write {
                             }
                         }
                     }
+                    // Wait until all data is shifted out
+                    while !self.read_flags().contains(Flags::TXC) {}
                     Ok(())
                 }
             }
@@ -666,6 +668,8 @@ macro_rules! impl_blocking_spi_write_iter {
                             }
                         }
                     }
+                    // Wait until all data is shifted out
+                    while !self.read_flags().contains(Flags::TXC) {}
                     Ok(())
                 }
             }
diff --git a/hal/src/sercom/spi/impl_ehal_thumbv7em.rs b/hal/src/sercom/spi/impl_ehal_thumbv7em.rs
index 8b106e63708..ddc05bf73d6 100644
--- a/hal/src/sercom/spi/impl_ehal_thumbv7em.rs
+++ b/hal/src/sercom/spi/impl_ehal_thumbv7em.rs
@@ -570,6 +570,8 @@ macro_rules! impl_blocking_spi_write {
                             }
                         }
                     }
+                    // Wait until all data is shifted out
+                    while !self.read_flags().contains(Flags::TXC) {}
                     Ok(())
                 }
             }
@@ -632,7 +634,10 @@ where
             panic!("Slice length does not equal SPI transfer length");
         }
         let sercom = unsafe { self.config.as_ref().sercom() };
-        write_slice(sercom, buf, false)
+        write_slice(sercom, buf, false)?;
+        // Wait until all data is shifted out
+        while !self.read_flags().contains(Flags::TXC) {}
+        Ok(())
     }
 }
 
@@ -687,7 +692,10 @@ where
             panic!("Slice length does not equal SPI transfer length");
         }
         let sercom = unsafe { self.config.as_ref().sercom() };
-        write_slice(sercom, buf, false)
+        write_slice(sercom, buf, false)?;
+        // Wait until all data is shifted out
+        while !self.read_flags().contains(Flags::TXC) {}
+        Ok(())
     }
 }
 
@@ -779,6 +787,8 @@ macro_rules! impl_blocking_spi_write_iter {
                             }
                         }
                     }
+                    // Wait until all data is shifted out
+                    while !self.read_flags().contains(Flags::TXC) {}
                     Ok(())
                 }
             }