FPGA implementation of the Data Encryption Standard algorithm, witten in VHDL. This module is not fully pipelined and thus targeted at low logic-block occupancy rather than maximal performances. Implemented on a DE-0 developpement board, interfaced with a Nios II soft processor (not included in this project).
978 register blocks, 511 LUT => less than 1% of Cyclone V SoC 5CSEMA5F31
85 MB/s