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Revert "PCI: rockchip: Add Rockchip DW PCIe controller support"
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This reverts commit 7cca3e2.
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@ayufan
ayufan committed May 25, 2019
1 parent 2a91b13 commit 2ea4fc1
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Showing 5 changed files with 16 additions and 1,311 deletions.
8 changes: 0 additions & 8 deletions drivers/pci/host/Kconfig
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Expand Up @@ -11,14 +11,6 @@ config PCI_DRA7XX
are two instances of PCIe controller in DRA7xx. This controller can
act both as EP and RC. This reuses the Designware core.

config PCIE_DW_ROCKCHIP
bool "Rockchip DesignWare PCIe controller"
select PCIE_DW
depends on ARCH_ROCKCHIP
depends on OF
help
Enables support for the DW PCIe controller in the Rockchip SoC.

config PCI_MVEBU
bool "Marvell EBU PCIe controller"
depends on ARCH_MVEBU || ARCH_DOVE
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1 change: 0 additions & 1 deletion drivers/pci/host/Makefile
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Expand Up @@ -21,4 +21,3 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie-dw-rockchip.o
89 changes: 16 additions & 73 deletions drivers/pci/host/pcie-designware.c
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Expand Up @@ -22,10 +22,25 @@
#include <linux/pci_regs.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/delay.h>

#include "pcie-designware.h"

/* Synopsis specific PCIE configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_MODE_MASK (0x3f << 16)
#define PORT_LINK_MODE_1_LANES (0x1 << 16)
#define PORT_LINK_MODE_2_LANES (0x3 << 16)
#define PORT_LINK_MODE_4_LANES (0x7 << 16)
#define PORT_LINK_MODE_8_LANES (0xf << 16)

#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)

#define PCIE_MSI_ADDR_LO 0x820
#define PCIE_MSI_ADDR_HI 0x824
#define PCIE_MSI_INTR0_ENABLE 0x828
Expand Down Expand Up @@ -136,67 +151,9 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
return ret;
}

static u32 dw_pcie_readl_ob_unroll(struct pcie_port *pp, u32 index, u32 reg)
{
u32 val;
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);

dw_pcie_readl_rc(pp, offset + reg, &val);

return val;
}

static void dw_pcie_writel_ob_unroll(struct pcie_port *pp, u32 index, u32 reg,
u32 val)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);

dw_pcie_writel_rc(pp, val, offset + reg);
}

static void dw_pcie_prog_outbound_atu_unroll(struct pcie_port *pp, int index,
int type, u64 cpu_addr,
u64 pci_addr, u32 size)
{
u32 retries, val;

dw_pcie_writel_ob_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE,
lower_32_bits(cpu_addr));
dw_pcie_writel_ob_unroll(pp, index, PCIE_ATU_UNR_UPPER_BASE,
upper_32_bits(cpu_addr));
dw_pcie_writel_ob_unroll(pp, index, PCIE_ATU_UNR_LIMIT,
lower_32_bits(cpu_addr + size - 1));
dw_pcie_writel_ob_unroll(pp, index, PCIE_ATU_UNR_LOWER_TARGET,
lower_32_bits(pci_addr));
dw_pcie_writel_ob_unroll(pp, index, PCIE_ATU_UNR_UPPER_TARGET,
upper_32_bits(pci_addr));
dw_pcie_writel_ob_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL1,
type);
dw_pcie_writel_ob_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL2,
PCIE_ATU_ENABLE);

/*
* Make sure ATU enable takes effect before any subsequent config
* and I/O accesses.
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
val = dw_pcie_readl_ob_unroll(pp, index,
PCIE_ATU_UNR_REGION_CTRL2);
if (val & PCIE_ATU_ENABLE)
return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
}
dev_err(pp->dev, "Outbound iATU is not being enabled\n");
}

static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
int type, u64 cpu_addr, u64 pci_addr, u32 size)
{
if (pp->iatu_unroll_enabled) {
dw_pcie_prog_outbound_atu_unroll(pp, index, type, cpu_addr,
pci_addr, size);
return;
}
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
Expand Down Expand Up @@ -748,18 +705,6 @@ static struct pci_ops dw_pcie_ops = {
.write = dw_pcie_wr_conf,
};

static u8 dw_pcie_iatu_unroll_enabled(struct pcie_port *pp)
{
u32 val;

dw_pcie_readl_rc(pp, PCIE_ATU_VIEWPORT, &val);
if (val == 0xffffffff) {
pr_info("dw_pcie_iatu_unroll enabled\n");
return 1;
}
return 0;
}

void dw_pcie_setup_rc(struct pcie_port *pp)
{
u32 val;
Expand Down Expand Up @@ -807,8 +752,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
}
dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);

pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);

/* setup RC BARs */
dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
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41 changes: 0 additions & 41 deletions drivers/pci/host/pcie-designware.h
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Original file line number Diff line number Diff line change
Expand Up @@ -22,49 +22,8 @@
#define MAX_MSI_IRQS 32
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)

/* Register address builder */
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
((0x3 << 20) | ((region) << 9))

#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
((0x3 << 20) | ((region) << 9) | (0x1 << 8))

/*
* iATU Unroll-specific register definitions
* From 4.80 core version the address translation will be made by unroll
*/
#define PCIE_ATU_UNR_REGION_CTRL1 0x00
#define PCIE_ATU_UNR_REGION_CTRL2 0x04
#define PCIE_ATU_UNR_LOWER_BASE 0x08
#define PCIE_ATU_UNR_UPPER_BASE 0x0C
#define PCIE_ATU_UNR_LIMIT 0x10
#define PCIE_ATU_UNR_LOWER_TARGET 0x14
#define PCIE_ATU_UNR_UPPER_TARGET 0x18

/* Parameters for the waiting for iATU enabled routine */
#define LINK_WAIT_MAX_IATU_RETRIES 5
#define LINK_WAIT_IATU_MIN 9000
#define LINK_WAIT_IATU_MAX 10000

/* Synopsis specific PCIE configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_MODE_MASK (0x3f << 16)
#define PORT_LINK_MODE_1_LANES (0x1 << 16)
#define PORT_LINK_MODE_2_LANES (0x3 << 16)
#define PORT_LINK_MODE_4_LANES (0x7 << 16)
#define PORT_LINK_MODE_8_LANES (0xf << 16)

#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)

struct pcie_port {
struct device *dev;
u8 iatu_unroll_enabled;
u8 root_bus_nr;
void __iomem *dbi_base;
u64 cfg0_base;
Expand Down
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