remove PSEUDO option

beardypig · Mar 21, 2019 · 484132a · 484132a
1 parent 81a4ac0
commit 484132a
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Showing 6 changed files with 20 additions and 26 deletions.
diff --git a/data/languages/base.sinc b/data/languages/base.sinc
@@ -179,8 +179,6 @@ RT32src: rt   	is rt & rt32=0      { export 0:4; }
 
 # relative offsets
 Rel16: reloc		is off16	[ reloc=inst_start+4+4*off16; ]					{ export *:4 reloc; }
-Rel21: reloc		is off21	[ reloc=inst_start+4+4*off21; ]					{ export *:4 reloc; }
-Rel26: reloc		is off26	[ reloc=inst_start+4+4*off26; ]					{ export *:4 reloc; }
 Abs26: reloc		is ind26	[ reloc=((inst_start+4) $and 0xfffffffff0000000) | 4*ind26; ]	{ export *:4 reloc; }
 
 OFF_BASE: simmed(base)  	is simmed & base    { tmp:4 = base:4 + simmed; export tmp; }
diff --git a/data/languages/eecore.sinc b/data/languages/eecore.sinc
@@ -2,9 +2,6 @@
 
 define register offset=0x400 size=8 [ fsa ];       # 64 bit
 
-define pcodeop loadQuadWord;
-define pcodeop storeQuadWord;
-define pcodeop storeQuadWordZero;
 define pcodeop PABSH;
 define pcodeop PABSW;
 define pcodeop PADDB;
@@ -98,15 +95,16 @@ define pcodeop PXOR;
 define pcodeop QFSRV;
 
 # 0111 10bb bbbt tttt iiii iiii iiii iiii
-:lq RT128, OFF_BASE                         is prime=30 & OFF_BASE & RT128 {
-    RT128 = loadQuadWord(OFF_BASE);
+:lq RT, OFF_BASE                         is prime=30 & OFF_BASE & RT {
+    RT = *:8 OFF_BASE;
 }
 
 # 0111 11bb bbbt tttt iiii iiii iiii iiii
-:sq RT128src, OFF_BASE                      is prime=31 & OFF_BASE & RT128src {
-    storeQuadWord(OFF_BASE, RT128src);
+:sq RTsrc, OFF_BASE                         is prime=31 & OFF_BASE & RTsrc {
+    *[ram]:8 OFF_BASE = RTsrc;
 }
 
+
 :mfsa RD                                    is prime=0 & RD & rs=0 & rt=0 & fct=40 {
     RD = fsa;
 }
@@ -333,13 +331,12 @@ with : prime=28 {
         hi = zext(prod:4);
     }
 
-
-@ifdef PSEUDO
-    # pseudo opcode, move quad word
-    :moveq RD128, RS128src                          is RS128src & RD128 & rt=0 & mmiop=24 & fct=40 {
-        RD128 = RS128src;
+    # special case of paddub, move quad word
+    # only operates on the 64 bit representations of the registers due to a 64 bit const varnode limitation
+    :moveq RD, RSsrc                                is RSsrc & RD & rt=0 & mmiop=24 & fct=40 {
+        RD = RSsrc;
     }
-@endif
+
 
     # PADDW
     :paddw RD128, RS128src, RT128src                is RS128src & RD128 & RT128src & mmiop=0 & fct=8 {

diff --git a/data/languages/emotionengine.ldefs b/data/languages/emotionengine.ldefs
@@ -5,12 +5,13 @@
             endian="little"
             size="32"
             variant="R5900-PS2"
-            version="1.3.0"
+            version="1.3.2"
             slafile="r5900.sla"
             processorspec="r5900.pspec"
             manualindexfile="../manuals/eecore.idx"
             id="r5900:LE:32:default">
     <description>Emotion Engine (Play Station 2) R5900 MIPS Core</description>
     <compiler name="default" spec="r5900.cspec" id="default"/>
-  </language> 
+    <external_name tool="DWARF.register.mapping.file" name="r5900.dwarf"/>
+  </language>
 </language_definitions>
diff --git a/data/languages/mips.sinc b/data/languages/mips.sinc
@@ -25,13 +25,12 @@ define pcodeop syscall;
     RT = sext(RT32);
 }
 
-@ifdef PSEUDO
-# 0010 01ss ssst tttt iiii iiii iiii iiii
+# 0010 0100 000t tttt iiii iiii iiii iiii
+# special case of ADDIU
 :li RT32, immed                         is prime=9 & RT32 & rs=0 & immed & RT {
     RT32 = zext(immed:2);
     RT = zext(RT32);
 }
-@endif
 
 # 0000 00ss ssst tttt dddd d000 0010 0001
 :addu RD32, RS32src, RT32src          	is prime=0 & zero5=0 & fct=33 & RS32src & RT32src & RD32 & RD {
@@ -193,12 +192,11 @@ define pcodeop syscall;
     RD = RSsrc + RTsrc;
 }
 
-@ifdef PSEUDO
 # pseudo opcode move (rd = rs + 0)
+# special case of DADDU
 :move RD, RSsrc                         is prime=0 & fct=45 & RSsrc & RD & rt=0 & zero5=0 {
     RD = RSsrc;
 }
-@endif
 
 # 0000 00ss ssst tttt 0000 0000 0001 1010
 :div RS32src, RT32src                   is prime=0 & fct=26 & zero10 & RS32src & RT32src {
@@ -458,12 +456,11 @@ define pcodeop syscall;
     RD = RSsrc | RTsrc;
 }
 
-@ifdef PSEUDO
 # pseudo opcode move (rd = rs OR 0)
+# special case of OR
 :move RD, RSsrc                         is prime=0 & fct=37 & RSsrc & rt=0 & RD & sa=0 {
     RD = RSsrc;
 }
-@endif
 
 # 0011 01ss ssst tttt iiii iiii iiii iiii
 :ori RT, RSsrc, immed           		is prime=13 & RSsrc & RT & immed  {

diff --git a/data/languages/r5900.pspec b/data/languages/r5900.pspec
@@ -1,5 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
 
 <processor_spec>
+  <properties>
+    <property key="addressesDoNotAppearDirectlyInCode" value="true"/>
+  </properties>
   <programcounter register="pc"/>
 </processor_spec>
diff --git a/data/languages/r5900.slaspec b/data/languages/r5900.slaspec
@@ -7,8 +7,6 @@
 #  4. COP1 (FPU) Instruction Set
 #  5. COP2 (VU) Macro Instruction Set
 
-@define PSEUDO "1"
-
 define endian=little;
 define alignment=2;