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fixup! Add unit test for the clock control Wishbone component. #5742

fixup! Add unit test for the clock control Wishbone component.

fixup! Add unit test for the clock control Wishbone component. #5742

Triggered via push October 24, 2024 12:42
Status Failure
Total duration 40m 59s
Artifacts 12

ci.yml

on: push
Build dependencies
2m 40s
Build dependencies
bittide-instances hardware-in-the-loop test matrix generation
19s
bittide-instances hardware-in-the-loop test matrix generation
bittide-instances synthesis matrix generation
18s
bittide-instances synthesis matrix generation
license-check
8s
license-check
Basic linting
29s
Basic linting
bittide-experiments unittests
56s
bittide-experiments unittests
Bittide tests
5m 11s
Bittide tests
Rust Lints
35s
Rust Lints
Firmware Support Unit Tests
2m 13s
Firmware Support Unit Tests
Host Tools Unit Tests
36s
Host Tools Unit Tests
Firmware Limit Checks
47s
Firmware Limit Checks
bittide-instances doctests
53s
bittide-instances doctests
bittide-instances unittests
1m 17s
bittide-instances unittests
Matrix: synth
Matrix: HITL
Generate clock control report
0s
Generate clock control report
All jobs finished
2s
All jobs finished
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Annotations

3 errors and 1 warning
Basic linting
Process completed with exit code 1.
Rust Lints
Process completed with exit code 1.
All jobs finished
Process completed with exit code 1.
HITL (linkConfigurationTest, test)
No files were found with the provided path: _build/vivado/*/ila-data _build/hitl/*. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
_build-fullMeshHwCcTest
130 MB
_build-fullMeshHwCcTest-debug
3.01 MB
_build-fullMeshSwCcTest
272 MB
_build-fullMeshSwCcTest-debug
3.93 MB
_build-linkConfigurationTest
12.4 MB
_build-safeDffSynchronizer
2.58 KB
_build-transceiversUpTest
192 MB
_build-transceiversUpTest-debug
1.96 MB
_build-vexRiscvTcpTest
48.1 MB
_build-vexRiscvTcpTest-debug
22 KB
_build-vexRiscvTest
40 MB
_build-vexRiscvTest-debug
22 KB