Add FINC/FDEC test #2466
ci.yml
on: push
Build dependencies
1m 15s
Basic linting
16s
elastic-buffer-sim-topologies simulation matrix generation
16s
bittide-instances hardware-in-the-loop test matrix generation
14s
bittide-instances synthesis matrix generation
17s
Firmware Build Examples
20s
elastic-buffer-sim unittests
2m 16s
Bittide tests
4m 28s
bittide-instances doctests
3m 4s
bittide-instances unittests
3m 13s
Matrix: Simulate network
Matrix: bittide-instances synthesis
Matrix: bittide-instances hardware-in-the-loop tests
All jobs finished
2s
Artifacts
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Clock Control Simulation Report
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50.3 KB |
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_build-clockControlDemo0
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13.9 MB |
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_build-extendedHardwareInTheLoopTest
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8.54 MB |
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_build-fincFdecTests
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12.1 MB |
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_build-simpleHardwareInTheLoopTest
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8.46 MB |
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gen-plots-hs-complete
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63.2 KB |
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