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[ | ||
{"top": "clockControlDemo0", "stage": "bitstream"}, | ||
{"top": "simpleHardwareInTheLoopTest", "stage": "test"}, | ||
{"top": "extendedHardwareInTheLoopTest", "stage": "test"} | ||
{"top": "extendedHardwareInTheLoopTest", "stage": "test"}, | ||
{"top": "fdecTest", "stage": "test"}, | ||
{"top": "simpleHardwareInTheLoopTest", "stage": "test"} | ||
] |
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# SPDX-FileCopyrightText: 2022-2023 Google LLC | ||
# | ||
# SPDX-License-Identifier: Apache-2.0 | ||
# | ||
# NOTE: This configuration is only valid for the leftmost FPGA in the demo rack. | ||
# | ||
# Color | FPGA pin | LVLShift | Connection | ||
# --------|---------------|---------------|--------- | ||
# Grey | PMOD0_0 | IO1 | SWDIO | ||
# Blue | PMOD0_1 | IO2 | FINC | ||
# Yellow | PMOD0_2 | IO3 | MOSI/SDIO | ||
# Red | PMOD0_3 | IO4 | SCLK | ||
# White | PMOD0_4 | IO5 | SWCLK | ||
# Purple | PMOD0_5 | IO6 | FDEC | ||
# Green | PMOD0_6 | IO7 | CSB | ||
# Orange | PMOD0_7 | IO8 | MISO/SDO | ||
# Black | Not connected | Not connected | GND (SWD) | ||
# Brown | PMOD_GND | GND | GND (SPI) | ||
# | ||
# The data wire of the external reset button is connected to PMOD1_3. | ||
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# CLK_125MHZ | ||
set_property BOARD_PART_PIN sysclk_125_p [get_ports {CLK_125MHZ_P}] | ||
set_property BOARD_PART_PIN sysclk_125_n [get_ports {CLK_125MHZ_N}] | ||
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# USER_SMA_CLOCK | ||
set_property -dict {IOSTANDARD LVDS PACKAGE_PIN D23} [get_ports {USER_SMA_CLOCK_P}] | ||
set_property -dict {IOSTANDARD LVDS PACKAGE_PIN C23} [get_ports {USER_SMA_CLOCK_N}] | ||
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# GPIO_LED_0_LS | ||
set_property BOARD_PART_PIN GPIO_LED_0_LS [get_ports {done}] | ||
# GPIO_LED_1_LS | ||
set_property BOARD_PART_PIN GPIO_LED_1_LS [get_ports {success}] | ||
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# PMOD0_[0..7] | ||
# set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AK25} [get_ports {SWDIO}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AN21} [get_ports {FINC}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AH18} [get_ports {MOSI}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM19} [get_ports {SCLK}] | ||
# set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE26} [get_ports {SWCLK}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AF25} [get_ports {FDEC}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE21} [get_ports {CSB}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM17} [get_ports {MISO}] |
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219 changes: 219 additions & 0 deletions
219
bittide-instances/src/Bittide/Instances/Tests/FincFdec.hs
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-- SPDX-FileCopyrightText: 2022-2023 Google LLC | ||
-- | ||
-- SPDX-License-Identifier: Apache-2.0 | ||
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{-# LANGUAGE NumericUnderscores #-} | ||
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-- | A couple of tests testing clock board programming, and subsequently the | ||
-- FINC and FDEC pins. | ||
module Bittide.Instances.Tests.FincFdec where | ||
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import Clash.Annotations.TH (makeTopEntity) | ||
import Clash.Explicit.Prelude | ||
import Clash.Prelude (withClockResetEnable) | ||
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import Bittide.Arithmetic.Time | ||
import Bittide.Counter (domainDiffCounter) | ||
import Bittide.ClockControl (SpeedChange(NoChange, SlowDown, SpeedUp), speedChangeToFincFdec) | ||
import Bittide.ClockControl.Si539xSpi (si539xSpi, ConfigState(Finished)) | ||
import Bittide.Instances.Domains | ||
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import Clash.Xilinx.ClockGen (clockWizardDifferential) | ||
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import Clash.Cores.Xilinx.Extra (ibufds) | ||
import Clash.Cores.Xilinx.VIO (vioProbe) | ||
import Clash.Cores.Xilinx.Xpm.Cdc.Single (xpmCdcSingle) | ||
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import qualified Bittide.ClockControl.Si5395J as Si5395J | ||
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data TestState = Busy | Fail | Success | ||
data Test = Fdec | Finc | ||
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testStateToDoneSuccess :: TestState -> (Bool, Bool) | ||
testStateToDoneSuccess = \case | ||
Busy -> (False, False) | ||
Fail -> (True, False) | ||
Success -> (True, True) | ||
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noReset :: KnownDomain dom => Reset dom | ||
noReset = unsafeFromHighPolarity (pure False) | ||
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eitherReset :: KnownDomain dom => Reset dom -> Reset dom -> Reset dom | ||
eitherReset (unsafeToHighPolarity -> rstA) (unsafeToHighPolarity -> rstB) = | ||
unsafeFromHighPolarity (rstA .||. rstB) | ||
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bothReset :: KnownDomain dom => Reset dom -> Reset dom -> Reset dom | ||
bothReset (unsafeToHighPolarity -> rstA) (unsafeToHighPolarity -> rstB) = | ||
unsafeFromHighPolarity (rstA .&&. rstB) | ||
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fdecTestGo :: | ||
Clock Basic200A -> | ||
Reset Basic200A -> | ||
Clock Basic200B -> | ||
Signal Basic200A Test -> | ||
"MISO" ::: Signal Basic200A Bit -> -- SPI | ||
"" ::: | ||
( Signal Basic200A TestState | ||
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-- Freq increase / freq decrease request to clock board | ||
, ( "FINC" ::: Signal Basic200A Bool | ||
, "FDEC" ::: Signal Basic200A Bool | ||
) | ||
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-- SPI to clock board: | ||
, "" ::: | ||
( "SCLK" ::: Signal Basic200A Bool | ||
, "MOSI" ::: Signal Basic200A Bit | ||
, "CSB" ::: Signal Basic200A Bool | ||
) | ||
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-- Debug signals: | ||
, "" ::: | ||
( "SPI_BUSY" ::: Signal Basic200A Bool | ||
, "SPI_STATE" ::: Signal Basic200A (BitVector 40) | ||
, "SI_LOCKED" ::: Signal Basic200A Bool | ||
, "COUNTER_ACTIVE" ::: Signal Basic200A Bool | ||
, "COUNTER" ::: Signal Basic200A (Signed 32) | ||
) | ||
) | ||
fdecTestGo clk rst clkControlled testSelect miso = | ||
(testResult, fIncDec, spiOut, debugSignals) | ||
where | ||
debugSignals = (spiBusy, pack <$> spiState, siClkLocked, counterActive, counter) | ||
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(_, spiBusy, spiState@(fmap (==Finished) -> siClkLocked), spiOut) = | ||
withClockResetEnable clk rst enableGen $ | ||
si539xSpi | ||
Si5395J.testConfig6_200_on_0a_and_0 | ||
-- Si5395J.testConfigAll200 | ||
(SNat @(Nanoseconds 1000)) | ||
(pure Nothing) | ||
miso | ||
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rstTest = unsafeFromLowPolarity siClkLocked | ||
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rstControlled = | ||
unsafeFromLowPolarity $ | ||
xpmCdcSingle clk clkControlled $ -- improvised reset syncer | ||
unsafeToLowPolarity rst | ||
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(counter, counterActive) = | ||
unbundle $ | ||
-- Note that in a "real" Bittide system the clocks would be wired up the | ||
-- other way around: the controlled domain would be the target domain. We | ||
-- don't do that here because we know 'rstControlled' will come out of | ||
-- reset much earlier than 'rstTest'. Doing it the "proper" way would | ||
-- therefore introduce extra complexity, without adding to the test's | ||
-- coverage. | ||
domainDiffCounter clkControlled rstControlled clk rstTest | ||
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fIncDec = unbundle $ speedChangeToFincFdec clk rst fIncDecRequest | ||
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(fIncDecRequest, testResult) = | ||
mealyB clk rstTest enableGen go () (counter, testSelect) | ||
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go :: () -> (Signed 32, Test) -> ((), (SpeedChange, TestState)) | ||
go () (n, Fdec) = ((), goFdec n) | ||
go () (n, Finc) = ((), goFinc n) | ||
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goFdec :: Signed 32 -> (SpeedChange, TestState) | ||
goFdec n | ||
| n > 20_000 = (NoChange, Fail) | ||
| n < -20_000 = (NoChange, Success) | ||
| otherwise = (SlowDown, Busy) | ||
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goFinc :: Signed 32 -> (SpeedChange, TestState) | ||
goFinc n | ||
| n > 20_000 = (NoChange, Success) | ||
| n < -20_000 = (NoChange, Fail) | ||
| otherwise = (SpeedUp, Busy) | ||
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fdecTest :: | ||
-- Pins from internal oscillator: | ||
"CLK_125MHZ_P" ::: Clock Basic125 -> | ||
"CLK_125MHZ_N" ::: Clock Basic125 -> | ||
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-- Pins from clock board: | ||
"USER_SMA_CLOCK_P" ::: Clock Basic200B -> | ||
"USER_SMA_CLOCK_N" ::: Clock Basic200B -> | ||
"MISO" ::: Signal Basic200A Bit -> -- SPI | ||
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"" ::: | ||
( "" ::: | ||
( "done" ::: Signal Basic200A Bool | ||
, "success" ::: Signal Basic200A Bool | ||
) | ||
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-- Freq increase / freq decrease request to clock board | ||
, "" ::: | ||
( "FINC" ::: Signal Basic200A Bool | ||
, "FDEC" ::: Signal Basic200A Bool | ||
) | ||
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-- SPI to clock board: | ||
, "" ::: | ||
( "SCLK" ::: Signal Basic200A Bool | ||
, "MOSI" ::: Signal Basic200A Bit | ||
, "CSB" ::: Signal Basic200A Bool | ||
) | ||
) | ||
fdecTest clkP clkN controlledClockP controlledClockN spiIn = | ||
((testDone, testSuccess), fIncDec, spiOut) | ||
where | ||
clkControlled = ibufds controlledClockP controlledClockN | ||
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(clk, clkStable0) = clockWizardDifferential (SSymbol @"pll") clkN clkP noReset | ||
clkStable1 = xpmCdcSingle clk clk clkStable0 -- improvised reset syncer | ||
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clkStableRst = unsafeFromLowPolarity clkStable1 | ||
startFdecTestRst = unsafeFromLowPolarity startFdecTest | ||
startFincTestRst = unsafeFromLowPolarity startFincTest | ||
testRst = eitherReset clkStableRst (bothReset startFdecTestRst startFincTestRst) | ||
testRstBool = unsafeToHighPolarity testRst | ||
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(fInc, fDec) = fIncDec | ||
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testF = mux startFdecTest (pure Fdec) (pure Finc) | ||
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(testResult, fIncDec, spiOut, debugSignals) = | ||
fdecTestGo clk testRst clkControlled testF spiIn | ||
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(testDone, testSuccess) = unbundle $ testStateToDoneSuccess <$> testResult | ||
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(spiBusy, spiState, siClkLocked, counterActive, counter) = debugSignals | ||
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(startFdecTest, startFincTest) = unbundle $ | ||
vioProbe | ||
( "probe_test_done" | ||
:> "probe_test_success" | ||
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-- Debug signals: | ||
:> "probe_clkStable1" | ||
:> "probe_testRstBool" | ||
:> "probe_spiBusy" | ||
:> "probe_spiState" | ||
:> "probe_siClkLocked" | ||
:> "probe_counterActive" | ||
:> "probe_counter" | ||
:> "probe_fInc" | ||
:> "probe_fDec" | ||
:> Nil) | ||
("probe_test_start_fdec" :> "probe_test_start_finc" :> Nil) | ||
(False, False) | ||
clk | ||
testDone | ||
testSuccess | ||
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-- Debug signals | ||
clkStable1 | ||
testRstBool | ||
spiBusy | ||
spiState | ||
siClkLocked | ||
counterActive | ||
counter | ||
fInc | ||
fDec | ||
{-# NOINLINE fdecTest #-} | ||
makeTopEntity 'fdecTest |
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