Clash 1.9 update (#444)

bittide · Jan 5, 2024 · 530a3a7 · 530a3a7
1 parent 735f33c
commit 530a3a7
Show file tree

Hide file tree

Showing 18 changed files with 179 additions and 190 deletions.
diff --git a/bittide-extra/bittide-extra.cabal b/bittide-extra/bittide-extra.cabal
@@ -63,7 +63,7 @@ common common-options
     Cabal,
     array,
     -- clash-prelude will set suitable version bounds for the plugins
-    clash-prelude >= 1.6.3 && < 1.8,
+    clash-prelude >= 1.6.3 && < 1.10,
     containers >= 0.4.0 && < 0.7,
     clash-protocols,
     ghc-typelits-extra,

diff --git a/bittide-instances/src/Bittide/Instances/Domains.hs b/bittide-instances/src/Bittide/Instances/Domains.hs
@@ -14,12 +14,15 @@ import Bittide.Arithmetic.Ppm
 import Data.Proxy
 
 createDomain vXilinxSystem{vName="Basic125", vPeriod= hzToPeriod 125e6}
+createDomain vXilinxSystem{vName="Ext125", vPeriod= hzToPeriod 125e6, vResetKind=Asynchronous}
 createDomain vXilinxSystem{vName="Basic25", vPeriod= hzToPeriod 25e6}
 createDomain vXilinxSystem{vName="Basic199", vPeriod=hzToPeriod 199e6}
 createDomain vXilinxSystem{vName="Basic200", vPeriod=hzToPeriod 200e6}
-createDomain vXilinxSystem{vName="Basic200A", vPeriod=hzToPeriod 200e6}
-createDomain vXilinxSystem{vName="Basic200B", vPeriod=hzToPeriod 200e6}
+createDomain vXilinxSystem{vName="Ext200", vPeriod=hzToPeriod 200e6, vResetKind=Asynchronous}
+createDomain vXilinxSystem{vName="Ext200A", vPeriod=hzToPeriod 200e6, vResetKind=Asynchronous}
+createDomain vXilinxSystem{vName="Ext200B", vPeriod=hzToPeriod 200e6, vResetKind=Asynchronous}
 createDomain vXilinxSystem{vName="Basic300", vPeriod=hzToPeriod 300e6}
+createDomain vXilinxSystem{vName="Ext300", vPeriod=hzToPeriod 300e6, vResetKind=Asynchronous}
 createDomain vXilinxSystem{vName="Basic50", vPeriod= hzToPeriod 50e6}
 createDomain vXilinxSystem{vName="External", vPeriod=hzToPeriod 200e6}
 createDomain vXilinxSystem{vName="GthRx", vPeriod=hzToPeriod 125e6}

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/BoardTest.hs b/bittide-instances/src/Bittide/Instances/Hitl/BoardTest.hs
@@ -55,8 +55,8 @@ check clk rst dut stimuli =
 -- | Testing circuit for `plus`. Feeds the circuit with inputs and checks
 -- the received output against the expected output.
 boardTestSimple ::
-  "CLK_125MHZ" ::: DiffClock Basic125 ->
-  "" ::: Signal Basic125
+  "CLK_125MHZ" ::: DiffClock Ext125 ->
+  "" ::: Signal Ext125
     ( "done" ::: Bool
     , "success" ::: Bool
     )
@@ -91,8 +91,8 @@ makeTopEntity 'boardTestSimple
 -- | Testing circuit for `plus` and `minus`. Feeds the circuit with inputs and
 -- checks the received output against the expected output.
 boardTestExtended ::
-  "CLK_125MHZ" ::: DiffClock Basic125 ->
-  "" ::: Signal Basic125
+  "CLK_125MHZ" ::: DiffClock Ext125 ->
+  "" ::: Signal Ext125
     ( "done" ::: Bool
     , "success" ::: Bool
     )
@@ -137,7 +137,7 @@ boardTestExtended diffClk = hwSeqX boardTestIla $ bundle (testDone, testSuccess)
       testSuccess
 
 
-  boardTestIla :: Signal Basic125 ()
+  boardTestIla :: Signal Ext125 ()
   boardTestIla =
     setName @"boardTestIla" $
     ila
@@ -154,7 +154,7 @@ boardTestExtended diffClk = hwSeqX boardTestIla $ bundle (testDone, testSuccess)
       -- Trigger when starting either test
       (testStartA .||. testStartB)
       -- Always capture
-      (pure True :: Signal Basic125 Bool)
+      (pure True :: Signal Ext125 Bool)
 
       -- Debug probes
       testStartA

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs b/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs
@@ -11,7 +11,6 @@ module Bittide.Instances.Hitl.FincFdec where
 import Clash.Annotations.TH (makeTopEntity)
 import Clash.Cores.Xilinx.Extra (ibufds)
 import Clash.Cores.Xilinx.VIO (vioProbe)
-import Clash.Cores.Xilinx.Xpm.Cdc.Single (xpmCdcSingle)
 import Clash.Explicit.Prelude
 import Clash.Prelude (withClockResetEnable)
 import Clash.Sized.Vector.Extra (findWithDefault)
@@ -54,34 +53,34 @@ testStateToDoneSuccess = \case
   Success -> (True, True)
 
 goFincFdecTests ::
-  Clock Basic200A ->
-  Reset Basic200A ->
-  Clock Basic200B ->
-  Signal Basic200A Test ->
-  "MISO" ::: Signal Basic200A Bit -> -- SPI
+  Clock Basic200 ->
+  Reset Basic200 ->
+  Clock Ext200 ->
+  Signal Basic200 Test ->
+  "MISO" ::: Signal Basic200 Bit -> -- SPI
   "" :::
-    ( Signal Basic200A TestState
+    ( Signal Basic200 TestState
 
     -- Freq increase / freq decrease request to clock board
     , "" :::
-      ( "FINC"    ::: Signal Basic200A Bool
-      , "FDEC"    ::: Signal Basic200A Bool
+      ( "FINC"    ::: Signal Basic200 Bool
+      , "FDEC"    ::: Signal Basic200 Bool
       )
 
       -- SPI to clock board:
     , "" :::
-      ( "SCLK" ::: Signal Basic200A Bool
-      , "MOSI" ::: Signal Basic200A Bit
-      , "CSB"  ::: Signal Basic200A Bool
+      ( "SCLK" ::: Signal Basic200 Bool
+      , "MOSI" ::: Signal Basic200 Bit
+      , "CSB"  ::: Signal Basic200 Bool
       )
 
       -- Debug signals:
     , "" :::
-      ( "SPI_BUSY" ::: Signal Basic200A Bool
-      , "SPI_STATE" ::: Signal Basic200A (BitVector 40)
-      , "SI_LOCKED" ::: Signal Basic200A Bool
-      , "COUNTER_ACTIVE" ::: Signal Basic200A Bool
-      , "COUNTER" ::: Signal Basic200A (Signed 32)
+      ( "SPI_BUSY" ::: Signal Basic200 Bool
+      , "SPI_STATE" ::: Signal Basic200 (BitVector 40)
+      , "SI_LOCKED" ::: Signal Basic200 Bool
+      , "COUNTER_ACTIVE" ::: Signal Basic200 Bool
+      , "COUNTER" ::: Signal Basic200 (Signed 32)
       )
     )
 goFincFdecTests clk rst clkControlled testSelect miso =
@@ -98,11 +97,7 @@ goFincFdecTests clk rst clkControlled testSelect miso =
         miso
 
   rstTest = unsafeFromActiveLow siClkLocked
-
-  rstControlled =
-    unsafeFromActiveLow $
-      xpmCdcSingle clk clkControlled $ -- improvised reset syncer
-        unsafeToActiveLow rst
+  rstControlled = convertReset clk clkControlled rst
 
   (counter, counterActive) =
     unbundle $
@@ -168,40 +163,39 @@ goFincFdecTests clk rst clkControlled testSelect miso =
 
 fincFdecTests ::
   -- Pins from internal oscillator:
-  "CLK_125MHZ" ::: DiffClock Basic125 ->
+  "CLK_125MHZ" ::: DiffClock Ext125 ->
 
   -- Pins from clock board:
-  "USER_SMA_CLOCK" ::: DiffClock Basic200B ->
-  "MISO" ::: Signal Basic200A Bit -> -- SPI
+  "USER_SMA_CLOCK" ::: DiffClock Ext200 ->
+  "MISO" ::: Signal Basic200 Bit -> -- SPI
 
   "" :::
     ( "" :::
-      ( "done"    ::: Signal Basic200A Bool
-      , "success" ::: Signal Basic200A Bool
+      ( "done"    ::: Signal Basic200 Bool
+      , "success" ::: Signal Basic200 Bool
       )
 
     -- Freq increase / freq decrease request to clock board
     , "" :::
-      ( "FINC"    ::: Signal Basic200A Bool
-      , "FDEC"    ::: Signal Basic200A Bool
+      ( "FINC"    ::: Signal Basic200 Bool
+      , "FDEC"    ::: Signal Basic200 Bool
       )
 
       -- SPI to clock board:
     , "" :::
-      ( "SCLK" ::: Signal Basic200A Bool
-      , "MOSI" ::: Signal Basic200A Bit
-      , "CSB"  ::: Signal Basic200A Bool
+      ( "SCLK" ::: Signal Basic200 Bool
+      , "MOSI" ::: Signal Basic200 Bit
+      , "CSB"  ::: Signal Basic200 Bool
       )
     )
 fincFdecTests diffClk controlledDiffClock spiIn =
   ((testDone, testSuccess), fIncDec, spiOut)
  where
   clkControlled = ibufds controlledDiffClock
 
-  (clk, clkStable0) = clockWizardDifferential (SSymbol @"pll") diffClk noReset
-  clkStable1 = xpmCdcSingle clk clk clkStable0 -- improvised reset syncer
+  (clk, clkStableRst) = clockWizardDifferential diffClk noReset
+  clkStable1 = unsafeToActiveLow clkStableRst
 
-  clkStableRst = unsafeFromActiveLow clkStable1
   anyStarted = fold (||) <$> startTests
   testRst = orReset clkStableRst (unsafeFromActiveLow anyStarted)
   testRstBool = unsafeToActiveHigh testRst
@@ -217,7 +211,7 @@ fincFdecTests diffClk controlledDiffClock spiIn =
 
   (spiBusy, spiState, siClkLocked, counterActive, counter) = debugSignals
 
-  startTests :: Signal Basic200A (Vec 4 Bool)
+  startTests :: Signal Basic200 (Vec 4 Bool)
   startTests =
     setName @"vioHitlt" $
     vioProbe

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs
@@ -205,7 +205,7 @@ fullMeshRiscvCopyTest clk rst callistoResult dataCounts = unbundle fIncDec
 -- be used to drive FINC/FDEC directly (see @FINC_FDEC@ result) or to tie the
 -- results to a RiscV core (see 'fullMeshRiscvCopyTest')
 fullMeshHwTest ::
-  "SMA_MGT_REFCLK_C" ::: Clock Basic200 ->
+  "SMA_MGT_REFCLK_C" ::: Clock Ext200 ->
   "SYSCLK" ::: Clock Basic125 ->
   "RST_LOCAL" ::: Reset Basic125 ->
   "ILA_CTRL" ::: IlaControl Basic125 ->
@@ -265,7 +265,7 @@ fullMeshHwTest refClk sysClk testRst IlaControl{..} rxns rxps miso =
 
   (head -> (txClock :: Clock GthTx), rxClocks, txns, txps, linkUpsRx, stats) = unzip6 $
     transceiverPrbsN
-      @GthTx @GthRx @Basic200 @Basic125 @GthTx @GthRx
+      @GthTx @GthRx @Ext200 @Basic125 @GthTx @GthRx
       refClk sysClk gthAllReset
       c_CHANNEL_NAMES c_CLOCK_PATHS rxns rxps
 
@@ -402,8 +402,8 @@ trueFor5s clk rst =
 
 -- | Top entity for this test. See module documentation for more information.
 fullMeshHwCcWithRiscvTest ::
-  "SMA_MGT_REFCLK_C" ::: DiffClock Basic200 ->
-  "SYSCLK_300" ::: DiffClock Basic300 ->
+  "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
+  "SYSCLK_300" ::: DiffClock Ext300 ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
   "GTH_RX_NS" ::: TransceiverWires GthRx ->
   "GTH_RX_PS" ::: TransceiverWires GthRx ->
@@ -425,12 +425,11 @@ fullMeshHwCcWithRiscvTest ::
 fullMeshHwCcWithRiscvTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   (txns, txps, (riscvFinc, riscvFdec), syncOut, spiDone, spiOut)
  where
-  refClk = ibufds_gte3 refClkDiff :: Clock Basic200
+  refClk = ibufds_gte3 refClkDiff :: Clock Ext200
+
+  (sysClk, sysRst0) = clockWizardDifferential sysClkDiff noReset
+  sysRst = sysRst0 `orReset` unsafeFromActiveLow startTest
 
-  (sysClk, sysLock0) = clockWizardDifferential (SSymbol @"SysClk") sysClkDiff noReset
-  sysLock1 = xpmCdcSingle sysClk sysClk sysLock0 -- improvised reset syncer
-  sysRst = unsafeFromActiveLow sysLock1
-    `orReset` unsafeFromActiveLow startTest
   --
   -- 'syncOutGenerator' is used to drive the 'SYNC_OUT' signal, which
   -- is only connected for the last node in the network and wired back
@@ -607,8 +606,8 @@ fullMeshHwCcWithRiscvTest refClkDiff sysClkDiff syncIn rxns rxps miso =
 
 -- | Top entity for this test. See module documentation for more information.
 fullMeshHwCcTest ::
-  "SMA_MGT_REFCLK_C" ::: DiffClock Basic200 ->
-  "SYSCLK_300" ::: DiffClock Basic300 ->
+  "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
+  "SYSCLK_300" ::: DiffClock Ext300 ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
   "GTH_RX_NS" ::: TransceiverWires GthRx ->
   "GTH_RX_PS" ::: TransceiverWires GthRx ->
@@ -630,12 +629,11 @@ fullMeshHwCcTest ::
 fullMeshHwCcTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   (txns, txps, unbundle hwFincFdecs, syncOut, spiDone, spiOut)
  where
-  refClk = ibufds_gte3 refClkDiff :: Clock Basic200
+  refClk = ibufds_gte3 refClkDiff :: Clock Ext200
+
+  (sysClk, sysRst0) = clockWizardDifferential sysClkDiff noReset
+  sysRst = sysRst0 `orReset` unsafeFromActiveLow startTest
 
-  (sysClk, sysLock0) = clockWizardDifferential (SSymbol @"SysClk") sysClkDiff noReset
-  sysLock1 = xpmCdcSingle sysClk sysClk sysLock0 -- improvised reset syncer
-  sysRst = unsafeFromActiveLow sysLock1
-    `orReset` unsafeFromActiveLow startTest
   --
   -- 'syncOutGenerator' is used to drive the 'SYNC_OUT' signal, which
   -- is only connected for the last node in the network and wired back

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
@@ -162,7 +162,7 @@ fullMeshRiscvTest clk rst dataCounts = unbundle fIncDec
 
 -- | Instantiates a hardware implementation of Callisto and exports its results.
 fullMeshHwTest ::
-  "SMA_MGT_REFCLK_C" ::: Clock Basic200 ->
+  "SMA_MGT_REFCLK_C" ::: Clock Ext200 ->
   "SYSCLK" ::: Clock Basic125 ->
   "RST_LOCAL" ::: Reset Basic125 ->
   "ILA_CTRL" ::: IlaControl Basic125 ->
@@ -222,7 +222,7 @@ fullMeshHwTest refClk sysClk testRst IlaControl{..} rxns rxps miso =
 
   (head -> (txClock :: Clock GthTx), rxClocks, txns, txps, linkUpsRx, stats) = unzip6 $
     transceiverPrbsN
-      @GthTx @GthRx @Basic200 @Basic125 @GthTx @GthRx
+      @GthTx @GthRx @Ext200 @Basic125 @GthTx @GthRx
       refClk sysClk gthAllReset
       c_CHANNEL_NAMES c_CLOCK_PATHS rxns rxps
 
@@ -359,8 +359,8 @@ trueFor5s clk rst =
 
 -- | Top entity for this test. See module documentation for more information.
 fullMeshSwCcTest ::
-  "SMA_MGT_REFCLK_C" ::: DiffClock Basic200 ->
-  "SYSCLK_300" ::: DiffClock Basic300 ->
+  "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
+  "SYSCLK_300" ::: DiffClock Ext300 ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
   "GTH_RX_NS" ::: TransceiverWires GthRx ->
   "GTH_RX_PS" ::: TransceiverWires GthRx ->
@@ -382,11 +382,10 @@ fullMeshSwCcTest ::
 fullMeshSwCcTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   (txns, txps, (riscvFinc, riscvFdec), syncOut, spiDone, spiOut)
  where
-  refClk = ibufds_gte3 refClkDiff :: Clock Basic200
+  refClk = ibufds_gte3 refClkDiff :: Clock Ext200
 
-  (sysClk, sysLock0) = clockWizardDifferential (SSymbol @"SysClk") sysClkDiff noReset
-  sysLock1 = xpmCdcSingle sysClk sysClk sysLock0 -- improvised reset syncer
-  sysRst = unsafeFromActiveLow sysLock1
+  (sysClk, sysRst0) = clockWizardDifferential sysClkDiff noReset
+  sysRst = sysRst0 `orReset` unsafeFromActiveLow startTest
 
   syncIn1 = (startTest .&&.)
     $ unsafeToActiveLow

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SyncInSyncOut.hs b/bittide-instances/src/Bittide/Instances/Hitl/SyncInSyncOut.hs
@@ -130,14 +130,13 @@ testStatusToDoneSuccess = \case
 
 -- | Entry point for test. See module documentation for more information.
 syncInSyncOut ::
-  "SYSCLK_300" ::: DiffClock Basic300 ->
+  "SYSCLK_300" ::: DiffClock Ext300 ->
   "SYNC_IN" ::: Signal Basic300 Bool ->
   "SYNC_OUT" ::: Signal Basic300 Bool
 syncInSyncOut sysClkDiff syncIn0 = syncOut
  where
-  (sysClk, sysLock0) = clockWizardDifferential (SSymbol @"pll") sysClkDiff noReset
-  sysLock1 = unsafeFromActiveLow (xpmCdcSingle sysClk sysClk sysLock0)
-  testRst = orReset sysLock1 (unsafeFromActiveLow startTest)
+  (sysClk, sysRst) = clockWizardDifferential sysClkDiff noReset
+  testRst = sysRst `orReset` (unsafeFromActiveLow startTest)
   syncIn1 =
       unsafeToActiveHigh
     $ resetGlitchFilter (SNat @1024) sysClk

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs b/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs
@@ -52,7 +52,7 @@ type TransceiverWires dom = Vec 7 (Signal dom (BitVector 1))
 -- | Worker function for 'transceiversUpTest'. See module documentation for more
 -- information.
 goTransceiversUpTest ::
-  "SMA_MGT_REFCLK_C" ::: Clock Basic200 ->
+  "SMA_MGT_REFCLK_C" ::: Clock Ext200 ->
   "SYSCLK" ::: Clock Basic125 ->
   "RST_LOCAL" ::: Reset Basic125 ->
   "GTH_RX_NS" ::: TransceiverWires GthRx ->
@@ -90,7 +90,7 @@ goTransceiversUpTest refClk sysClk rst rxns rxps miso =
 
   (_txClocks, rxClocks, txns, txps, linkUpsRx, stats) = unzip6 $
     transceiverPrbsN
-      @GthTx @GthRx @Basic200 @Basic125 @GthTx @GthRx
+      @GthTx @GthRx @Ext200 @Basic125 @GthTx @GthRx
       refClk sysClk gthAllReset
       c_CHANNEL_NAMES c_CLOCK_PATHS rxns rxps
 
@@ -115,8 +115,8 @@ trueFor50s clk rst =
 
 -- | Top entity for this test. See module documentation for more information.
 transceiversUpTest ::
-  "SMA_MGT_REFCLK_C" ::: DiffClock Basic200 ->
-  "SYSCLK_300" ::: DiffClock Basic300 ->
+  "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
+  "SYSCLK_300" ::: DiffClock Ext300 ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
   "GTH_RX_NS" ::: TransceiverWires GthRx ->
   "GTH_RX_PS" ::: TransceiverWires GthRx ->
@@ -134,11 +134,10 @@ transceiversUpTest ::
 transceiversUpTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   (txns, txps, syncOut, spiDone, spiOut)
  where
-  refClk = ibufds_gte3 refClkDiff :: Clock Basic200
+  refClk = ibufds_gte3 refClkDiff :: Clock Ext200
+
+  (sysClk, sysRst) = clockWizardDifferential sysClkDiff noReset
 
-  (sysClk, sysLock0) = clockWizardDifferential (SSymbol @"SysClk") sysClkDiff noReset
-  sysLock1 = xpmCdcSingle sysClk sysClk sysLock0 -- improvised reset syncer
-  sysRst = unsafeFromActiveLow sysLock1
   testRst = sysRst `orReset` unsafeFromActiveLow startTest `orReset` syncInRst
   syncOut = startTest
   syncInRst =