From 8560f30e47305ab9255fd2cbe403a9d324b098d0 Mon Sep 17 00:00:00 2001
From: Hidde Moll <hidde@qbaylogic.com>
Date: Mon, 29 Apr 2024 10:24:25 +0200
Subject: [PATCH] Add ILA to `i2cWb` and debug print statements to fmc-clock
 binary

---
 bittide/src/Bittide/Wishbone.hs         | 54 ++++++++++++++++++++++++-
 firmware-binaries/fmc-clock/src/main.rs | 25 +++++++++++-
 2 files changed, 75 insertions(+), 4 deletions(-)

diff --git a/bittide/src/Bittide/Wishbone.hs b/bittide/src/Bittide/Wishbone.hs
index 8a7520da1..dfd70ad7b 100644
--- a/bittide/src/Bittide/Wishbone.hs
+++ b/bittide/src/Bittide/Wishbone.hs
@@ -16,7 +16,7 @@ import Bittide.SharedTypes
 
 import Clash.Cores.UART (uart, ValidBaud)
 import Clash.Cores.Experimental.I2C
-import Clash.Cores.Xilinx.Ila (ila, ilaConfig, IlaConfig(..), Depth)
+import Clash.Cores.Xilinx.Ila (ila, ilaConfig, IlaConfig(..), Depth (..))
 import Clash.Sized.Vector.ToTuple
 import Clash.Util.Interpolate
 
@@ -492,7 +492,7 @@ i2cWb ::
 i2cWb = case (cancelMulDiv @nBytes @8) of
   Dict -> Circuit go
     where
-      go ((wbM2S, i2cIn), _) = ((wbS2M, pure ()), i2cOut)
+      go ((wbM2S, i2cIn), _) =  i2cWbIla `hwSeqX` ((wbS2M, pure ()), i2cOut)
        where
         -- Wishbone interface consists of:
         -- 0. i2c data Read-Write
@@ -531,6 +531,56 @@ i2cWb = case (cancelMulDiv @nBytes @8) of
         (dOut,hostAck,busy,al,ackOut,i2cOut) =
           i2c hasClock hasReset smReset (fromEnable hasEnable) clkDiv claimBus i2cOp ackIn i2cIn
 
+        onChange :: (HiddenClockResetEnable dom, Eq a, NFDataX a) => Signal dom a -> Signal dom Bool
+        onChange x = (Just <$> x) ./=. register Nothing (Just <$> x)
+
+        capture :: Signal dom Bool
+        capture = withClockResetEnable hasClock hasReset enableGen $
+          onChange $ bundle
+            ( isJust <$> i2cOp
+            , wbAck
+            , flagsRead
+            , isJust <$> transAddr
+            , hostAck
+            , busy
+            , al
+            , ackOut
+            , ackIn
+            , claimBus
+            )
+
+        i2cWbIla :: Signal dom ()
+        i2cWbIla = setName @"i2cWbIla" $ ila
+          ((ilaConfig $
+               "trigger_2"
+            :> "capture_2"
+            :> "i2cOp"
+            :> "wbAck"
+            :> "flagsRead"
+            :> "transAddr"
+            :> "hostAck"
+            :> "busy"
+            :> "al"
+            :> "ackOut"
+            :> "ackIn"
+            :> "claimBus"
+            :> Nil
+          ) { depth = D16384 })
+          hasClock
+          (pure True :: Signal dom Bool)
+          capture
+          -- Debug signals
+          i2cOp
+          wbAck
+          flagsRead
+          transAddr
+          hostAck
+          busy
+          al
+          ackOut
+          ackIn
+          claimBus
+
 -- Wishbone accessible register circuit which can only be written to from the circuit.
 statusRegWb ::
   forall dom a nBytes addrW .
diff --git a/firmware-binaries/fmc-clock/src/main.rs b/firmware-binaries/fmc-clock/src/main.rs
index 0decb7068..de82f728a 100644
--- a/firmware-binaries/fmc-clock/src/main.rs
+++ b/firmware-binaries/fmc-clock/src/main.rs
@@ -187,13 +187,22 @@ pub fn configure_clock_chip(
     for line in si534x_config.lines() {
         if !parser.is_done() {
             let old_state = parser.state;
-            if let Ok(Some(ConfigEntry { page, addr, data })) = parser.parse_line(line) {
-                si534x.write_byte(page, addr, data)?;
+            match parser.parse_line(line) {
+                Ok(Some(ConfigEntry { page, addr, data })) => {
+                    si534x.write_byte(page, addr, data)?;
+                    uwriteln!(uart, "Wrote: {:2X} {:2X} {:2X}", page, addr, data).unwrap();
+                }
+                Ok(None) => {}
+                Err(e) => {
+                    uwriteln!(uart, "Error: {:?}", e).unwrap();
+                }
             }
             if old_state == ParserState::Preamble && parser.state == ParserState::PostPreambleDelay
             {
                 // Wait 300ms after writing the preamble
+                uwriteln!(uart, "Waiting 300 ms after preamble...").unwrap();
                 clock.wait(Duration::from_millis(300));
+                uwriteln!(uart, "Done waiting").unwrap();
             }
         }
     }
@@ -221,6 +230,18 @@ fn main() -> ! {
         control_reg.set_clock_init_done();
     }
 
+    // Try to read and write the page number
+    match si534x.read_byte(0x0, 0x01) {
+        Ok(d) => uwriteln!(uart, "Current page: {:2X}", d).unwrap(),
+        Err(e) => uwriteln!(uart, "ERROR: {:?}", e).unwrap(),
+    }
+    _ = si534x.set_page(0x1);
+    match si534x.read_byte(0x1, 0x01) {
+        Ok(d) => uwriteln!(uart, "Current page: {:2X}", d).unwrap(),
+        Err(e) => uwriteln!(uart, "ERROR: {:?}", e).unwrap(),
+    }
+    uwriteln!(uart, "Checked pages, continuing...").unwrap();
+
     // Do the FInc FDec tests
     let mut last_status_reg;
     let mut sub_test = Test::Idle;