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Squashed 'clash-vexriscv/' changes from 390818c9..0ac4a4f7
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0ac4a4f7 Merge pull request #36 from clash-lang/lucas/add-Jtag-Idle
31e1b754 Add `IdleCircuit` for `Jtag`
dab50530 Bump `clash-protocols` dependency

git-subtree-dir: clash-vexriscv
git-subtree-split: 0ac4a4f754055ea8d9f61471843ce0c83b0cbddd
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lmbollen committed Sep 24, 2024
1 parent 98c7997 commit acf5d7b
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Showing 4 changed files with 16 additions and 1 deletion.
1 change: 1 addition & 0 deletions bittide/bittide.cabal
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Expand Up @@ -100,6 +100,7 @@ library
clash-lib >=1.6.3 && <1.10,
clash-prelude >=1.6.3 && <1.10,
clash-protocols,
clash-protocols-base,
clash-vexriscv,
constraints >=0.13.3 && <0.15,
containers >=0.4.0 && <0.7,
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9 changes: 8 additions & 1 deletion cabal.project
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Expand Up @@ -174,7 +174,14 @@ source-repository-package
source-repository-package
type: git
location: https://github.com/clash-lang/clash-protocols.git
tag: 623ecd9658fa5b15f71b0d86bac6b714b4b86dc4
tag: 0832a422e77422739401896f6612620d17baa289
subdir: clash-protocols

source-repository-package
type: git
location: https://github.com/clash-lang/clash-protocols.git
tag: 0832a422e77422739401896f6612620d17baa289
subdir: clash-protocols-base

source-repository-package
type: git
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2 changes: 2 additions & 0 deletions cabal.project.freeze
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Expand Up @@ -73,6 +73,8 @@ constraints: any.Cabal ==3.10.3.0,
any.clash-prelude-hedgehog ==1.9.0,
any.clash-protocols ==0.1,
clash-protocols -ci -large-tuples,
any.clash-protocols-base ==0.1,
clash-protocols-base -ci -large-tuples,
any.clock ==0.8.4,
clock -llvm,
any.cmdargs ==0.10.22,
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5 changes: 5 additions & 0 deletions clash-vexriscv/clash-vexriscv/src/VexRiscv.hs
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Expand Up @@ -27,6 +27,7 @@ import GHC.IO (unsafePerformIO, unsafeInterleaveIO)
import GHC.Stack (HasCallStack)
import Language.Haskell.TH.Syntax
import Protocols
import Protocols.Idle
import Protocols.Wishbone

import VexRiscv.ClockTicks
Expand Down Expand Up @@ -72,6 +73,10 @@ instance Protocol (Jtag dom) where
type Fwd (Jtag dom) = Signal dom JtagIn
type Bwd (Jtag dom) = Signal dom JtagOut

instance IdleCircuit (Jtag dom) where
idleFwd _ = pure $ JtagIn 0 0 0
idleBwd _ = pure $ JtagOut 0 0

vexRiscv ::
forall dom .
( HasCallStack
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