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Merge pull request #316 from bittide/fincfdectest
Add FINC/FDEC hiw-test
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[ | ||
{"top": "callisto3", "stage": "netlist"}, | ||
{"top": "counterReducedPins", "stage": "netlist"}, | ||
{"top": "clockControlDemo0", "stage": "bitstream"}, | ||
{"top": "clockControlDemo1", "stage": "bitstream"}, | ||
{"top": "counterReducedPins", "stage": "netlist"}, | ||
{"top": "elasticBuffer5", "stage": "netlist"}, | ||
{"top": "extendedHardwareInTheLoopTest", "stage": "test"}, | ||
{"top": "gatherUnit1K", "stage": "hdl" }, | ||
{"top": "gatherUnit1K", "stage": "hdl"}, | ||
{"top": "gatherUnit1KReducedPins", "stage": "netlist"}, | ||
{"top": "simpleHardwareInTheLoopTest", "stage": "test"}, | ||
{"top": "safeDffSynchronizer", "stage": "netlist"}, | ||
{"top": "scatterUnit1K", "stage": "hdl" }, | ||
{"top": "scatterUnit1K", "stage": "hdl"}, | ||
{"top": "scatterUnit1KReducedPins", "stage": "netlist"}, | ||
{"top": "si5391Spi", "stage": "netlist"}, | ||
{"top": "stabilityChecker_3_1M", "stage": "netlist"}, | ||
{"top": "switchCalendar1k", "stage": "hdl" }, | ||
{"top": "switchCalendar1kReducedPins", "stage": "netlist"} | ||
{"top": "switchCalendar1k", "stage": "hdl"}, | ||
{"top": "switchCalendar1kReducedPins", "stage": "netlist"}, | ||
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{"top": "extendedHardwareInTheLoopTest", "stage": "test", "targets": "All" }, | ||
{"top": "fincFdecTests", "stage": "test", "targets": "Specific [-1]"}, | ||
{"top": "simpleHardwareInTheLoopTest", "stage": "test", "targets": "All" } | ||
] |
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[ | ||
{"top": "clockControlDemo0", "stage": "bitstream"}, | ||
{"top": "simpleHardwareInTheLoopTest", "stage": "test"}, | ||
{"top": "extendedHardwareInTheLoopTest", "stage": "test"} | ||
{"top": "extendedHardwareInTheLoopTest", "stage": "test", "targets": "All"}, | ||
{"top": "fincFdecTests", "stage": "test", "targets": "Specific [-1]"}, | ||
{"top": "simpleHardwareInTheLoopTest", "stage": "test", "targets": "All"} | ||
] |
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-- SPDX-FileCopyrightText: 2022-2023 Google LLC | ||
-- | ||
-- SPDX-License-Identifier: Apache-2.0 | ||
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module Clash.Reset.Extra where | ||
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import Clash.Explicit.Prelude | ||
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-- TODO: Remove these functions after merging clash-compiler#2539 | ||
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-- | A reset that is never asserted | ||
noReset :: KnownDomain dom => Reset dom | ||
noReset = unsafeFromActiveHigh (pure False) | ||
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-- | Output reset will be asserted when either one of the input resets is | ||
-- asserted | ||
orReset :: | ||
forall dom . | ||
( KnownDomain dom | ||
, DomainResetKind dom ~ 'Synchronous ) => | ||
Reset dom -> | ||
Reset dom -> | ||
Reset dom | ||
orReset = unsafeOrReset | ||
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-- | Output reset will be asserted when both input resets are asserted | ||
andReset :: | ||
forall dom . | ||
( KnownDomain dom | ||
, DomainResetKind dom ~ 'Synchronous ) => | ||
Reset dom -> | ||
Reset dom -> | ||
Reset dom | ||
andReset = unsafeAndReset | ||
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-- | Output reset will be asserted when both input resets are asserted. This | ||
-- function is considered unsafe because it can be used on domains with | ||
-- components whose resets are level sensitive, while use of this function can | ||
-- introduce glitches. | ||
unsafeAndReset :: forall dom. KnownDomain dom => Reset dom -> Reset dom -> Reset dom | ||
unsafeAndReset (unsafeFromReset -> rst0) (unsafeFromReset -> rst1) = | ||
unsafeToReset $ | ||
case resetPolarity @dom of | ||
SActiveHigh -> rst0 .&&. rst1 | ||
SActiveLow -> rst0 .||. rst1 | ||
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-- | Output reset will be asserted when either one of the input resets is | ||
-- asserted. This function is considered unsafe because it can be used on | ||
-- domains with components whose resets are level sensitive, while use of this | ||
-- function can introduce glitches. | ||
unsafeOrReset :: forall dom. KnownDomain dom => Reset dom -> Reset dom -> Reset dom | ||
unsafeOrReset (unsafeFromReset -> rst0) (unsafeFromReset -> rst1) = | ||
unsafeToReset $ | ||
case resetPolarity @dom of | ||
SActiveHigh -> rst0 .||. rst1 | ||
SActiveLow -> rst0 .&&. rst1 |
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-- SPDX-FileCopyrightText: 2022-2023 Google LLC | ||
-- | ||
-- SPDX-License-Identifier: Apache-2.0 | ||
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module Clash.Sized.Vector.Extra where | ||
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import Clash.Explicit.Prelude | ||
import Data.Maybe (fromMaybe) | ||
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-- | Finds first element in given vector matching the predicate. Returns | ||
-- 'Nothing' if no element satisfied the predicate. | ||
find :: KnownNat n => (a -> Bool) -> Vec n a -> Maybe a | ||
find f = foldl (<|>) Nothing . map go | ||
where | ||
go a | ||
| f a = Just a | ||
| otherwise = Nothing | ||
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-- | Finds first element in given vector matching the predicate. Returns a | ||
-- default element (the first argument) if no element satisfied the predicate. | ||
findWithDefault :: KnownNat n => a -> (a -> Bool) -> Vec n a -> a | ||
findWithDefault a f = fromMaybe a . find f |
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# SPDX-FileCopyrightText: 2022-2023 Google LLC | ||
# | ||
# SPDX-License-Identifier: Apache-2.0 | ||
# | ||
# NOTE: This configuration is only valid for the leftmost FPGA in the demo rack. | ||
# | ||
# Color | FPGA pin | LVLShift | Connection | ||
# --------|---------------|---------------|--------- | ||
# Grey | PMOD0_0 | IO1 | SWDIO | ||
# Blue | PMOD0_1 | IO2 | FINC | ||
# Yellow | PMOD0_2 | IO3 | MOSI/SDIO | ||
# Red | PMOD0_3 | IO4 | SCLK | ||
# White | PMOD0_4 | IO5 | SWCLK | ||
# Purple | PMOD0_5 | IO6 | FDEC | ||
# Green | PMOD0_6 | IO7 | CSB | ||
# Orange | PMOD0_7 | IO8 | MISO/SDO | ||
# Black | Not connected | Not connected | GND (SWD) | ||
# Brown | PMOD_GND | GND | GND (SPI) | ||
# | ||
# The data wire of the external reset button is connected to PMOD1_3. | ||
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# CLK_125MHZ | ||
set_property BOARD_PART_PIN sysclk_125_p [get_ports {CLK_125MHZ_p}] | ||
set_property BOARD_PART_PIN sysclk_125_n [get_ports {CLK_125MHZ_n}] | ||
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# USER_SMA_CLOCK | ||
set_property -dict {IOSTANDARD LVDS PACKAGE_PIN D23} [get_ports {USER_SMA_CLOCK_p}] | ||
set_property -dict {IOSTANDARD LVDS PACKAGE_PIN C23} [get_ports {USER_SMA_CLOCK_n}] | ||
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# GPIO_LED_0_LS | ||
set_property BOARD_PART_PIN GPIO_LED_0_LS [get_ports {done}] | ||
# GPIO_LED_1_LS | ||
set_property BOARD_PART_PIN GPIO_LED_1_LS [get_ports {success}] | ||
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# PMOD0_[0..7] | ||
# set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AK25} [get_ports {SWDIO}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AN21} [get_ports {FINC}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AH18} [get_ports {MOSI}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM19} [get_ports {SCLK}] | ||
# set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE26} [get_ports {SWCLK}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AF25} [get_ports {FDEC}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE21} [get_ports {CSB}] | ||
set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM17} [get_ports {MISO}] |
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