From d420ced9370bea6116ac65b2d5c9ecc034129265 Mon Sep 17 00:00:00 2001
From: Ryan Slawson <ryan@qbaylogic.com>
Date: Tue, 22 Oct 2024 17:05:59 +0200
Subject: [PATCH] Previous errors may have been caused by attempting to
 transmit to nodes that weren't ready.

---
 .../Bittide/Instances/Hitl/SwCcTopologies.hs   | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
index 3d01fc549..c0c56e4c8 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
@@ -261,10 +261,12 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
     withClockResetEnable sysClk syncRst enableGen
       $ si539xSpi commonSpiConfig (SNat @(Microseconds 10)) (pure Nothing) miso
 
-  -- Transceiver setup
-  gthAllReset = unsafeFromActiveLow clocksAdjusted
-
-  txReady = unsafeSynchronizer sysClk (head transceivers.txClocks) notInCCReset
+  txReady0 :: Vec LinkCount (Signal Basic125 Bool)
+  txReady0 = fmap go transceivers.linkReadys
+   where
+    go lR = lR .&&. notInCCReset -- if lR then notInCCReset else False
+  txReady1 :: Vec LinkCount (Signal GthTx Bool)
+  txReady1 = zipWith (unsafeSynchronizer sysClk) transceivers.txClocks txReady0
 
   transceivers =
     transceiverPrbsN
@@ -277,7 +279,7 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
       Transceiver.defConfig
       Transceiver.Inputs
         { clock = sysClk
-        , reset = gthAllReset
+        , reset = syncRst
         , refClock = refClk
         , channelNames
         , clockPaths
@@ -287,7 +289,7 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
         -- , txReadys = txAllStables
         -- , rxReadys = repeat (pure True)
         , txDatas = repeat (pure 0)
-        , txReadys = repeat txReady
+        , txReadys = txReady1
         , rxReadys = repeat (pure True)
         }
 
@@ -393,7 +395,7 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
           :> "probe_dDiff5"
           :> "probe_dDiff6"
           :> "probe_syncRst"
-          :> "probe_gthAllReset"
+          -- :> "probe_gthAllReset"
           :> "probe_startupDelayRst"
           :> "probe_clockControlReset"
           :> "probe_notInCCReset"
@@ -464,7 +466,7 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
       dDiff5
       dDiff6
       (unsafeFromReset syncRst)
-      (unsafeFromReset gthAllReset)
+      -- (unsafeFromReset gthAllReset)
       (unsafeFromReset startupDelayRst)
       (unsafeFromReset clockControlReset)
       notInCCReset