Add FINC/FDEC HITL-test

.github/synthesis/all.json

@@ -1,18 +1,21 @@
 [
   {"top": "callisto3",                     "stage": "netlist"},
-  {"top": "counterReducedPins",            "stage": "netlist"},
   {"top": "clockControlDemo0",             "stage": "bitstream"},
   {"top": "clockControlDemo1",             "stage": "bitstream"},
+  {"top": "counterReducedPins",            "stage": "netlist"},
   {"top": "elasticBuffer5",                "stage": "netlist"},
   {"top": "extendedHardwareInTheLoopTest", "stage": "test"},
-  {"top": "gatherUnit1K",                  "stage": "hdl"    },
+  {"top": "gatherUnit1K",                  "stage": "hdl"},
   {"top": "gatherUnit1KReducedPins",       "stage": "netlist"},
-  {"top": "simpleHardwareInTheLoopTest",   "stage": "test"},
   {"top": "safeDffSynchronizer",           "stage": "netlist"},
-  {"top": "scatterUnit1K",                 "stage": "hdl"    },
+  {"top": "scatterUnit1K",                 "stage": "hdl"},
   {"top": "scatterUnit1KReducedPins",      "stage": "netlist"},
   {"top": "si5391Spi",                     "stage": "netlist"},
   {"top": "stabilityChecker_3_1M",         "stage": "netlist"},
-  {"top": "switchCalendar1k",              "stage": "hdl"    },
-  {"top": "switchCalendar1kReducedPins",   "stage": "netlist"}
+  {"top": "switchCalendar1k",              "stage": "hdl"},
+  {"top": "switchCalendar1kReducedPins",   "stage": "netlist"},
+
+  {"top": "extendedHardwareInTheLoopTest", "stage": "test",   "targets": "All"          },
+  {"top": "fincFdecTests",                 "stage": "test",   "targets": "Specific [-1]"},
+  {"top": "simpleHardwareInTheLoopTest",   "stage": "test",   "targets": "All"          }
 ]

.github/synthesis/staging.json

@@ -1,5 +1,6 @@
 [
   {"top": "clockControlDemo0",             "stage": "bitstream"},
-  {"top": "simpleHardwareInTheLoopTest",   "stage": "test"},
-  {"top": "extendedHardwareInTheLoopTest", "stage": "test"}
+  {"top": "extendedHardwareInTheLoopTest", "stage": "test", "targets": "All"},
+  {"top": "fincFdecTests",                 "stage": "test", "targets": "Specific [-1]"},
+  {"top": "simpleHardwareInTheLoopTest",   "stage": "test", "targets": "All"}
 ]

.github/workflows/ci.yml

@@ -731,7 +731,7 @@ jobs:
             dir=$(ls _build/vivado | grep -E '\.${{ matrix.target.top }}$')
             tcl_test=_build/vivado/"${dir}"/run_hardware_test.tcl
             tcl_program=_build/vivado/"${dir}"/run_board_program.tcl
-            cabal run shake -- "${tcl_test}" "${tcl_program}" --hardware-targets=All
+            cabal run shake -- "${tcl_test}" "${tcl_program}" --hardware-targets="${{ matrix.target.targets }}"
           fi
 
       - name: Archive build artifacts

bittide-extra/bittide-extra.cabal

@@ -75,6 +75,8 @@ library
   exposed-modules:
     Bittide.Extra.Maybe
     Bittide.Extra.Wishbone
+    Clash.Reset.Extra
+    Clash.Sized.Vector.Extra
 
 test-suite doctests
   type:             exitcode-stdio-1.0

bittide-extra/src/Clash/Reset/Extra.hs

@@ -0,0 +1,56 @@
+-- SPDX-FileCopyrightText: 2022-2023 Google LLC
+--
+-- SPDX-License-Identifier: Apache-2.0
+
+module Clash.Reset.Extra where
+
+import Clash.Explicit.Prelude
+
+-- TODO: Remove these functions after merging clash-compiler#2539
+
+-- | A reset that is never asserted
+noReset :: KnownDomain dom => Reset dom
+noReset = unsafeFromActiveHigh (pure False)
+
+-- | Output reset will be asserted when either one of the input resets is
+-- asserted
+orReset ::
+  forall dom .
+  ( KnownDomain dom
+  , DomainResetKind dom ~ 'Synchronous ) =>
+  Reset dom ->
+  Reset dom ->
+  Reset dom
+orReset = unsafeOrReset
+
+-- | Output reset will be asserted when both input resets are asserted
+andReset ::
+  forall dom .
+  ( KnownDomain dom
+  , DomainResetKind dom ~ 'Synchronous ) =>
+  Reset dom ->
+  Reset dom ->
+  Reset dom
+andReset = unsafeAndReset
+
+-- | Output reset will be asserted when both input resets are asserted. This
+-- function is considered unsafe because it can be used on domains with
+-- components whose resets are level sensitive, while use of this function can
+-- introduce glitches.
+unsafeAndReset :: forall dom. KnownDomain dom => Reset dom -> Reset dom -> Reset dom
+unsafeAndReset (unsafeFromReset -> rst0) (unsafeFromReset -> rst1) =
+  unsafeToReset $
+    case resetPolarity @dom of
+      SActiveHigh -> rst0 .&&. rst1
+      SActiveLow  -> rst0 .||. rst1
+
+-- | Output reset will be asserted when either one of the input resets is
+-- asserted. This function is considered unsafe because it can be used on
+-- domains with components whose resets are level sensitive, while use of this
+-- function can introduce glitches.
+unsafeOrReset :: forall dom. KnownDomain dom => Reset dom -> Reset dom -> Reset dom
+unsafeOrReset (unsafeFromReset -> rst0) (unsafeFromReset -> rst1) =
+  unsafeToReset $
+    case resetPolarity @dom of
+      SActiveHigh -> rst0 .||. rst1
+      SActiveLow  -> rst0 .&&. rst1

bittide-extra/src/Clash/Sized/Vector/Extra.hs

@@ -0,0 +1,22 @@
+-- SPDX-FileCopyrightText: 2022-2023 Google LLC
+--
+-- SPDX-License-Identifier: Apache-2.0
+
+module Clash.Sized.Vector.Extra where
+
+import Clash.Explicit.Prelude
+import Data.Maybe (fromMaybe)
+
+-- | Finds first element in given vector matching the predicate. Returns
+-- 'Nothing' if no element satisfied the predicate.
+find :: KnownNat n => (a -> Bool) -> Vec n a -> Maybe a
+find f = foldl (<|>) Nothing . map go
+ where
+  go a
+    | f a = Just a
+    | otherwise = Nothing
+
+-- | Finds first element in given vector matching the predicate. Returns a
+-- default element (the first argument) if no element satisfied the predicate.
+findWithDefault :: KnownNat n => a -> (a -> Bool) -> Vec n a -> a
+findWithDefault a f = fromMaybe a . find f

bittide-instances/bin/Shake.hs

@@ -36,6 +36,9 @@ import qualified Bittide.Instances.ScatterGather as ScatterGather
 import qualified Bittide.Instances.Si539xSpi as Si539xSpi
 import qualified Bittide.Instances.StabilityChecker as StabilityChecker
 import qualified Bittide.Instances.Synchronizer as Synchronizer
+
+import qualified Bittide.Instances.Tests.FincFdec as FincFdec
+
 import qualified Clash.Util.Interpolate as I
 import qualified Language.Haskell.TH as TH
 import qualified System.Directory as Directory
@@ -159,6 +162,14 @@ defTarget name = Target
   , targetHasTest = False
   }
 
+testTarget :: TH.Name -> Target
+testTarget name = Target
+  { targetName = name
+  , targetHasXdc = True
+  , targetHasVio = True
+  , targetHasTest = True
+  }
+
 enforceValidTarget :: Target -> Target
 enforceValidTarget target@Target{..}
   | targetHasTest && not targetHasVio =
@@ -170,17 +181,7 @@ enforceValidTarget target@Target{..}
 -- | All synthesizable targets
 targets :: [Target]
 targets = map enforceValidTarget
-  [ (defTarget 'BoardTest.simpleHardwareInTheLoopTest)
-    { targetHasXdc = True
-    , targetHasVio = True
-    , targetHasTest = True
-    }
-  , (defTarget 'BoardTest.extendedHardwareInTheLoopTest)
-    { targetHasXdc = True
-    , targetHasVio = True
-    , targetHasTest = True
-    }
-  , defTarget 'Calendar.switchCalendar1k
+  [ defTarget 'Calendar.switchCalendar1k
   , defTarget 'Calendar.switchCalendar1kReducedPins
   , defTarget 'ClockControl.callisto3
   , defTarget 'Counter.counterReducedPins
@@ -195,6 +196,10 @@ targets = map enforceValidTarget
   , defTarget 'Si539xSpi.si5391Spi
   , defTarget 'StabilityChecker.stabilityChecker_3_1M
   , defTarget 'Synchronizer.safeDffSynchronizer
+
+  , testTarget 'BoardTest.extendedHardwareInTheLoopTest
+  , testTarget 'BoardTest.simpleHardwareInTheLoopTest
+  , testTarget 'FincFdec.fincFdecTests
   ]
 
 shakeOpts :: ShakeOptions

bittide-instances/bittide-instances.cabal

@@ -111,6 +111,9 @@ library
     Bittide.Instances.StabilityChecker
     Bittide.Instances.Synchronizer
 
+    -- Hardware-in-the-loop tests
+    Bittide.Instances.Tests.FincFdec
+
     Clash.Shake.Extra
     Clash.Shake.Flags
     Clash.Shake.Vivado

bittide-instances/data/constraints/fincFdecTests.xdc

@@ -0,0 +1,44 @@
+# SPDX-FileCopyrightText: 2022-2023 Google LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# NOTE: This configuration is only valid for the leftmost FPGA in the demo rack.
+#
+# Color   | FPGA pin      | LVLShift      | Connection
+# --------|---------------|---------------|---------
+# Grey    | PMOD0_0       | IO1           | SWDIO
+# Blue    | PMOD0_1       | IO2           | FINC
+# Yellow  | PMOD0_2       | IO3           | MOSI/SDIO
+# Red     | PMOD0_3       | IO4           | SCLK
+# White   | PMOD0_4       | IO5           | SWCLK
+# Purple  | PMOD0_5       | IO6           | FDEC
+# Green   | PMOD0_6       | IO7           | CSB
+# Orange  | PMOD0_7       | IO8           | MISO/SDO
+# Black   | Not connected | Not connected | GND (SWD)
+# Brown   | PMOD_GND      | GND           | GND (SPI)
+#
+# The data wire of the external reset button is connected to PMOD1_3.
+
+
+# CLK_125MHZ
+set_property BOARD_PART_PIN sysclk_125_p [get_ports {CLK_125MHZ_p}]
+set_property BOARD_PART_PIN sysclk_125_n [get_ports {CLK_125MHZ_n}]
+
+# USER_SMA_CLOCK
+set_property -dict {IOSTANDARD LVDS PACKAGE_PIN D23} [get_ports {USER_SMA_CLOCK_p}]
+set_property -dict {IOSTANDARD LVDS PACKAGE_PIN C23} [get_ports {USER_SMA_CLOCK_n}]
+
+# GPIO_LED_0_LS
+set_property BOARD_PART_PIN GPIO_LED_0_LS [get_ports {done}]
+# GPIO_LED_1_LS
+set_property BOARD_PART_PIN GPIO_LED_1_LS [get_ports {success}]
+
+# PMOD0_[0..7]
+# set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AK25} [get_ports {SWDIO}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AN21} [get_ports {FINC}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AH18} [get_ports {MOSI}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM19} [get_ports {SCLK}]
+# set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE26} [get_ports {SWCLK}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AF25} [get_ports {FDEC}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE21} [get_ports {CSB}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM17} [get_ports {MISO}]

bittide-instances/data/tcl/HardwareTest.tcl

@@ -17,7 +17,7 @@ set fpga_ids {
 
 # Timeout specifying how long we should wait for a test to finish before
 # considering it a failed test.
-set test_timeout_ms 1000
+set test_timeout_ms 60000
 
 # Timeout specifying how long to wait for hardware targets (FPGAs) to become
 # available in the hardware server.