Add in a software clock control DUT

[rslawson]

This PR adds in a new SwCc DUT based on the work done in my two other PRs. As of the current PR it mostly passes CI except for linting, but that's okay since there's still work to be done.

As for what work is still yet to be done:

• @lmbollen suggested that I add in UGN stability testing to this test as well. It was in some earlier versions of my work, which can be seen in the (awful) history of my rs/measure-sw-cc branch. The only other DUT this appears in is FullMeshSwCc.
• Some work must be done to figure out why I need the weird hack around masking syncIn to IlaPlotSetup (see line 908 and lines 937-947 as of time of writing) in order to avoid two syncRst asserts, which then causes captureCond to become Calibrate :: CaptureCondition for a second time, which is problematic.
• Commented-out legacy code needs to be removed.
• Formatting needs to be fixed (thanks CI).

[rslawson]

I should also probably report that somewhere in the combined total of the work from the three PRs (between this one and the two it depends on) the clock update frequency variability mentioned in issue #587 seems to have disappeared. Looking at the callistoSwIla ILA data, every test reports a minimum update period of 307 cycles/2.456 μs and a maximum update period of 309 cycles/2.472 μs for a variability of 16 ns. This is consistent across all boards within all topologies. The only big unknown left is software reframing timing, but that should be easy enough to get data on with just a single change to the DUT in another branch.

[rslawson]

As per the discussion in the meeting earlier today, the syncIn masking hack will stay in place until the testing framework changes in the pre-process branch are merged.

The issue is, as far as I can tell, that the syncOut signal from FPGA 7 continues to propagate to the other boards until it is reset by the HITL VIO providing it with new test data. The other boards, are still receiving this on syncIn, causing them to begin the test early. This results in the plotting ILA entering the calibrating state twice per test, which is a problem for cc-plot.

The current hack solution in this branch looks for the syncIn signal to be unchanging for 25ms or longer, which is interpreted as FPGA 7 being reset. After this the syncIn signal is unmasked and allowed to propagate through to the test synchronisation circuitry for the duration of the test. However, through proper usage of the pre-test, monitor, and post-test functions in the HITL tests it should be possible to force all of the synchronisers into reset in the post-test phase. This would ensure there would be no sync signal on syncIn until all of the boards have been given test data in the following pre-test phase.

[rslawson]

Adding to work to be done:
Figure out a way to make sure that each node cannot run a diff clock against another node that has not left clock control reset.