A novel FPGA PD 3.1 140W Trigger Design

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This project is an extented work from https://github.com/briansune/USB-PD-Verilog

This example demonstrate a PD 3.1 Trigger design via FPGA internal LVDS and external buffer IC.

The output voltage is set to 28V.

Anlogic FPGA (Spartan 7 is broke during high voltage test)

Reference Links:

1: https://www.usbzh.com/article/detail-368.html

2: http://kevinzhengwork.blogspot.com/2014/09/usb-power-delivery-protocol-layer.html

3: https://www.embedded.com/usb-type-c-and-power-delivery-101-power-delivery-protocol/

4: https://usbchargingblog.wordpress.com/2020/02/22/how-to-sniff-pd-source-capability-and-monitor-pd-negotiations-without-a-pd-analyzer/

5: https://www.chromium.org/chromium-os/twinkie/

6: https://blog.csdn.net/xp562870732/article/details/108501283