top_tb.v

`include "top.v"

module test;

reg clk = 0;

// To use the test bench with iverilog you will need to switch the 24 mHz clock
// to a clk generated by the test bench as the simulation of the pll does not
// generate a clock. Other than the clock there are no other inputs.

top uut (
	.clk(clk)
);

initial begin
	$dumpfile("top_tb.vcd");
	$dumpvars(0, uut);
	# 600000;
	$finish;
end

always #1 clk = !clk;

endmodule // test