GitHub - casper-astro/xml2vhdl: Python code to generate AXI4Lite VHDL register interfaces and Interconnect from a XML memory map specification.

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Python code to generate AXI4Lite VHDL register interfaces and Interconnect from a XML memory map specification.

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Name		Name	Last commit message	Last commit date
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docs		docs
scripts/python/xml2vhdl-ox		scripts/python/xml2vhdl-ox
.gitignore		.gitignore
LICENSE		LICENSE

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Copyright (C) 2015-2019
University of Oxford <http://www.ox.ac.uk/>
Department of Physics

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, version 3.

This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.