From 19cc7773baf2e3a06f0aa886f22b1185872f2fbe Mon Sep 17 00:00:00 2001 From: "Sergio R. Caprile" Date: Mon, 25 Mar 2024 10:11:22 -0300 Subject: [PATCH] silence pedantic new versions --- mongoose.c | 6 +++--- src/drivers/ra.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/mongoose.c b/mongoose.c index 0ffd4d68d8f..7350ec69df8 100644 --- a/mongoose.c +++ b/mongoose.c @@ -14825,7 +14825,7 @@ static uint16_t smi_rd(uint16_t header) { pir = 0; // read, mdc = 0 ETHERC->PIR = pir; raspin(s_smispin / 2); // 1/4 clock period, 300ns max access time - data |= ETHERC->PIR & MG_BIT(3) ? 1 : 0; // read mdio + data |= ETHERC->PIR & MG_BIT(3) ? 1U : 0; // read mdio raspin(s_smispin / 2); // 1/4 clock period pir |= MG_BIT(0); // mdc = 1 ETHERC->PIR = pir; @@ -14835,11 +14835,11 @@ static uint16_t smi_rd(uint16_t header) { } static uint16_t raeth_read_phy(uint8_t addr, uint8_t reg) { - return smi_rd((1 << 14) | (2 << 12) | (addr << 7) | (reg << 2) | (2 << 0)); + return smi_rd((1U << 14) | (2U << 12) | (addr << 7) | (reg << 2) | (2U << 0)); } static void raeth_write_phy(uint8_t addr, uint8_t reg, uint16_t val) { - smi_wr((1 << 14) | (1 << 12) | (addr << 7) | (reg << 2) | (2 << 0), val); + smi_wr((1U << 14) | (1U << 12) | (addr << 7) | (reg << 2) | (2U << 0), val); } // MDC clock is generated manually; as per 802.3, it must not exceed 2.5MHz diff --git a/src/drivers/ra.c b/src/drivers/ra.c index 459a320d4e1..93d0dcd95a3 100644 --- a/src/drivers/ra.c +++ b/src/drivers/ra.c @@ -101,7 +101,7 @@ static uint16_t smi_rd(uint16_t header) { pir = 0; // read, mdc = 0 ETHERC->PIR = pir; raspin(s_smispin / 2); // 1/4 clock period, 300ns max access time - data |= ETHERC->PIR & MG_BIT(3) ? 1 : 0; // read mdio + data |= ETHERC->PIR & MG_BIT(3) ? 1U : 0; // read mdio raspin(s_smispin / 2); // 1/4 clock period pir |= MG_BIT(0); // mdc = 1 ETHERC->PIR = pir; @@ -111,11 +111,11 @@ static uint16_t smi_rd(uint16_t header) { } static uint16_t raeth_read_phy(uint8_t addr, uint8_t reg) { - return smi_rd((1 << 14) | (2 << 12) | (addr << 7) | (reg << 2) | (2 << 0)); + return smi_rd((1U << 14) | (2U << 12) | (addr << 7) | (reg << 2) | (2U << 0)); } static void raeth_write_phy(uint8_t addr, uint8_t reg, uint16_t val) { - smi_wr((1 << 14) | (1 << 12) | (addr << 7) | (reg << 2) | (2 << 0), val); + smi_wr((1U << 14) | (1U << 12) | (addr << 7) | (reg << 2) | (2U << 0), val); } // MDC clock is generated manually; as per 802.3, it must not exceed 2.5MHz