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../../../mongoose.c |
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../../../mongoose.h |
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#pragma once | ||
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#define MG_ARCH MG_ARCH_NEWLIB // Use ARM toolchain | ||
#define MG_ENABLE_TCPIP 1 // Enable built-in network stack | ||
#define MG_ENABLE_DRIVER_RT1020 1 // Enable RTxx driver | ||
#define MG_ENABLE_CUSTOM_MILLIS 1 // Let user implement mg_millis() | ||
#define MG_ENABLE_FILE 0 // Disable POSIX filesystem | ||
#define MG_ENABLE_PACKED_FS 1 // Enable packed filesystem | ||
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#define HTTP_URL "http://0.0.0.0" | ||
#define HTTPS_URL "https://0.0.0.0" |
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../../device-dashboard/net.c |
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../../device-dashboard/net.h |
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../../device-dashboard/packed_fs.c |
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#include "mongoose.h" | ||
#include "net.h" | ||
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#define GENERATE_MAC_ADDRESS() \ | ||
{ \ | ||
2, (uint8_t) (HW_OCOTP_CFG0 & 255), \ | ||
(uint8_t) ((HW_OCOTP_CFG0 >> 10) & 255), \ | ||
(uint8_t) (((HW_OCOTP_CFG0 >> 19) ^ (HW_OCOTP_CFG1 >> 19)) & 255), \ | ||
(uint8_t) ((HW_OCOTP_CFG1 >> 10) & 255), \ | ||
(uint8_t) (HW_OCOTP_CFG1 & 255) \ | ||
} | ||
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uint64_t mg_millis(void) { // Let Mongoose use our uptime function | ||
return millis(); | ||
} | ||
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void setup() { | ||
pinMode(LED_BUILTIN, OUTPUT); | ||
Serial.begin(115200); | ||
while (!Serial) (void) 0; | ||
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struct mg_mgr mgr; // Initialise | ||
mg_mgr_init(&mgr); // Mongoose event manager | ||
mg_log_set(MG_LL_DEBUG); // Set log level | ||
mg_log_set_fn([](char ch, void *) { Serial.print(ch); }, NULL); | ||
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MG_INFO(("Starting TCP/IP stack..., CPU %g", (double) F_CPU / 1000000)); | ||
// Initialise Mongoose network stack | ||
ethernet_init(); | ||
struct mg_tcpip_driver_rt1020_data driver_data = {.mdc_cr = 24, | ||
.phy_addr = 0}; | ||
struct mg_tcpip_if mif = {.mac = GENERATE_MAC_ADDRESS(), | ||
// Uncomment below for static configuration: | ||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)), | ||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)), | ||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)), | ||
.driver = &mg_tcpip_driver_rt1020, | ||
.driver_data = &driver_data}; | ||
mg_tcpip_init(&mgr, &mif); | ||
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web_init(&mgr); // Initialise Web dashboard | ||
for (;;) mg_mgr_poll(&mgr, 0); // Run event loop | ||
} | ||
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void loop() { | ||
} | ||
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extern "C" { | ||
extern void (*volatile _VectorsRam[176])(void); | ||
extern void ENET_IRQHandler(void); | ||
}; | ||
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set)) | ||
#define RMII_PAD_INPUT_PULLDOWN 0x30E9 | ||
#define RMII_PAD_INPUT_PULLUP 0xB0E9 | ||
#define RMII_PAD_CLOCK 0x0031 | ||
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// initialize the ethernet hardware | ||
static void ethernet_init(void) { | ||
CCM_CCGR1 |= CCM_CCGR1_ENET(CCM_CCGR_ON); | ||
// configure PLL6 for 50 MHz, pg 1173 | ||
CCM_ANALOG_PLL_ENET_CLR = | ||
CCM_ANALOG_PLL_ENET_POWERDOWN | CCM_ANALOG_PLL_ENET_BYPASS | 0x0F; | ||
CCM_ANALOG_PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE | | ||
CCM_ANALOG_PLL_ENET_BYPASS | ||
/*| CCM_ANALOG_PLL_ENET_ENET2_REF_EN*/ | ||
| CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN | ||
/*| CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(1)*/ | ||
| CCM_ANALOG_PLL_ENET_DIV_SELECT(1); | ||
while (!(CCM_ANALOG_PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK)) | ||
; // wait for PLL lock | ||
CCM_ANALOG_PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS; | ||
// configure REFCLK to be driven as output by PLL6, pg 326 | ||
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CLRSET(IOMUXC_GPR_GPR1, | ||
IOMUXC_GPR_GPR1_ENET1_CLK_SEL | IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN, | ||
IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR); | ||
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// Configure pins | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 5; // Reset B0_14 Alt5 GPIO7.15 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 5; // Power B0_15 Alt5 GPIO7.14 | ||
GPIO7_GDIR |= (1 << 14) | (1 << 15); | ||
GPIO7_DR_SET = (1 << 15); // power on | ||
GPIO7_DR_CLEAR = (1 << 14); // reset PHY chip | ||
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = RMII_PAD_INPUT_PULLDOWN; // PhyAdd[0] = 0 | ||
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = RMII_PAD_INPUT_PULLDOWN; // PhyAdd[1] = 1 | ||
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = | ||
RMII_PAD_INPUT_PULLUP; // Master/Slave = slave mode | ||
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = | ||
RMII_PAD_INPUT_PULLDOWN; // Auto MDIX Enable | ||
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = RMII_PAD_INPUT_PULLUP; | ||
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = RMII_PAD_INPUT_PULLUP; | ||
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = RMII_PAD_INPUT_PULLUP; | ||
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = RMII_PAD_CLOCK; | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 3; // RXD1 B1_05 Alt3, pg 525 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 3; // RXD0 B1_04 Alt3, pg 524 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 6 | 0x10; // REFCLK B1_10 Alt6, pg 530 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 3; // RXER B1_11 Alt3, pg 531 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 3; // RXEN B1_06 Alt3, pg 526 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 3; // TXEN B1_09 Alt3, pg 529 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 3; // TXD0 B1_07 Alt3, pg 527 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 3; // TXD1 B1_08 Alt3, pg 528 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 0; // MDIO B1_15 Alt0, pg 535 | ||
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 0; // MDC B1_14 Alt0, pg 534 | ||
IOMUXC_ENET_MDIO_SELECT_INPUT = 2; // GPIO_B1_15_ALT0, pg 792 | ||
IOMUXC_ENET0_RXDATA_SELECT_INPUT = 1; // GPIO_B1_04_ALT3, pg 792 | ||
IOMUXC_ENET1_RXDATA_SELECT_INPUT = 1; // GPIO_B1_05_ALT3, pg 793 | ||
IOMUXC_ENET_RXEN_SELECT_INPUT = 1; // GPIO_B1_06_ALT3, pg 794 | ||
IOMUXC_ENET_RXERR_SELECT_INPUT = 1; // GPIO_B1_11_ALT3, pg 795 | ||
IOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 1; // GPIO_B1_10_ALT6, pg 791 | ||
delay(1); | ||
GPIO7_DR_SET = (1 << 14); // start PHY chip | ||
ENET_MSCR = ENET_MSCR_MII_SPEED(9); | ||
delay(1); | ||
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// Setup IRQ handler | ||
_VectorsRam[16 + IRQ_ENET] = ENET_IRQHandler; | ||
NVIC_ENABLE_IRQ(IRQ_ENET); | ||
} | ||
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