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standardize example names #2327

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Aug 2, 2023
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standardize example names #2327

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4 changes: 2 additions & 2 deletions .github/workflows/test.yml
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Expand Up @@ -225,11 +225,11 @@ jobs:
- path: esp8266/http-client-server
- path: stm32/nucleo-f429zi-make-baremetal-builtin
- path: stm32/nucleo-f429zi-make-freertos-builtin
- path: stm32/nucleo-f429zi-rndis
- path: stm32/nucleo-f429zi-make-baremetal-builtin-rndis
- path: stm32/nucleo-f746zg-make-baremetal-builtin
- path: stm32/nucleo-f746zg-make-freertos-builtin
- path: stm32/nucleo-f746zg-freertos-tcp
- path: stm32/nucleo-f746zg-rndis
- path: stm32/nucleo-f746zg-make-baremetal-builtin-rndis
- path: stm32/nucleo-h743zi-make-baremetal-builtin
- path: nxp/nxp-mimxrt1020-azurertos
- path: nxp/nxp-frdmk66f-freertos
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0 examples/stm32/nucleo-f429zi-rndis/Makefile → ...9zi-make-baremetal-builtin-rndis/Makefile
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3 changes: 3 additions & 0 deletions examples/stm32/nucleo-f429zi-make-baremetal-builtin-rndis/README.md
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@@ -0,0 +1,3 @@
# RNDIS Web device dashboard on NUCLEO-F429ZI

See https://mongoose.ws/tutorials/stm32/all-make-baremetal-builtin-rndis/
21 changes: 21 additions & 0 deletions examples/stm32/nucleo-f429zi-rndis/hal.h → ...f429zi-make-baremetal-builtin-rndis/hal.h
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Expand Up @@ -17,6 +17,13 @@
#define PINNO(pin) (pin & 255)
#define PINBANK(pin) (pin >> 8)

#define LED1 PIN('B', 0) // On-board LED pin (green)
#define LED2 PIN('B', 7) // On-board LED pin (blue)
#define LED3 PIN('B', 14) // On-board LED pin (red)

#define LED LED2 // Use blue LED for blinking

// System clock
// 6.3.3: APB1 clock <= 45MHz; APB2 clock <= 90MHz
// 3.5.1, Table 11: configure flash latency (WS) in accordance to clock freq
// 33.4: The AHB clock must be at least 25 MHz when Ethernet is used
Expand Down Expand Up @@ -121,6 +128,20 @@ static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
return (uint8_t) (uart->DR & 255);
}

static inline void usb_init() {
gpio_init(PIN('A', 11), GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 10); // D+
gpio_init(PIN('A', 12), GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 10); // D-
gpio_init(PIN('A', 9), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 0); // VBUS
gpio_init(PIN('A', 10), GPIO_MODE_AF, GPIO_OTYPE_OPEN_DRAIN, GPIO_SPEED_HIGH,
GPIO_PULL_UP, 10); // ID
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; // Enable USB FS clock
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; // VBUS sensing disable
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // VBUS sensing enable
}

static inline void rng_init(void) {
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
RNG->CR |= RNG_CR_RNGEN;
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0 examples/stm32/nucleo-f429zi-rndis/link.ld → ...29zi-make-baremetal-builtin-rndis/link.ld
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11 changes: 1 addition & 10 deletions examples/stm32/nucleo-f746zg-rndis/main.c → ...429zi-make-baremetal-builtin-rndis/main.c
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Expand Up @@ -5,7 +5,6 @@
#include "mongoose.h"
#include "tusb.h"

#define LED PIN('B', 7) // On-board LED pin (blue)
static struct mg_tcpip_if *s_ifp;
const uint8_t tud_network_mac_address[6] = {2, 2, 0x84, 0x6A, 0x96, 0};

Expand Down Expand Up @@ -101,15 +100,7 @@ int main(void) {
mg_http_listen(&mgr, "tcp://0.0.0.0:80", fn, &mgr);

MG_INFO(("Init USB ..."));
gpio_init(PIN('A', 11), GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 10); // D+
gpio_init(PIN('A', 12), GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 10); // D-
gpio_init(PIN('A', 9), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 0); // VBUS
gpio_init(PIN('A', 10), GPIO_MODE_AF, GPIO_OTYPE_OPEN_DRAIN, GPIO_SPEED_HIGH,
GPIO_PULL_UP, 10); // ID
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; // Enable USB FS clock
usb_init();
tusb_init();

MG_INFO(("Init done, starting main loop ..."));
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0 ...ples/stm32/nucleo-f429zi-rndis/mongoose.c → ...i-make-baremetal-builtin-rndis/mongoose.c
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0 ...ples/stm32/nucleo-f429zi-rndis/mongoose.h → ...i-make-baremetal-builtin-rndis/mongoose.h
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0 ...tm32/nucleo-f429zi-rndis/netif/ethernet.h → ...-baremetal-builtin-rndis/netif/ethernet.h
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0 ...ples/stm32/nucleo-f429zi-rndis/syscalls.c → ...i-make-baremetal-builtin-rndis/syscalls.c
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0 examples/stm32/nucleo-f429zi-rndis/sysinit.c → ...zi-make-baremetal-builtin-rndis/sysinit.c
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0 ...s/stm32/nucleo-f429zi-rndis/tusb_config.h → ...ake-baremetal-builtin-rndis/tusb_config.h
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0 ...m32/nucleo-f429zi-rndis/usb_descriptors.c → ...baremetal-builtin-rndis/usb_descriptors.c
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3 changes: 0 additions & 3 deletions examples/stm32/nucleo-f429zi-rndis/README.md
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0 examples/stm32/nucleo-f746zg-rndis/Makefile → ...6zg-make-baremetal-builtin-rndis/Makefile
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3 changes: 3 additions & 0 deletions examples/stm32/nucleo-f746zg-make-baremetal-builtin-rndis/README.md
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@@ -0,0 +1,3 @@
# RNDIS Web device dashboard on NUCLEO-F746ZG

See https://mongoose.ws/tutorials/stm32/all-make-baremetal-builtin-rndis/
18 changes: 18 additions & 0 deletions examples/stm32/nucleo-f746zg-rndis/hal.h → ...f746zg-make-baremetal-builtin-rndis/hal.h
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Expand Up @@ -17,6 +17,12 @@
#define PINNO(pin) (pin & 255)
#define PINBANK(pin) (pin >> 8)

#define LED1 PIN('B', 0) // On-board LED pin (green)
#define LED2 PIN('B', 7) // On-board LED pin (blue)
#define LED3 PIN('B', 14) // On-board LED pin (red)

#define LED LED2 // Use blue LED for blinking

/* System clock
5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz
3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq
Expand Down Expand Up @@ -123,6 +129,18 @@ static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
return (uint8_t) (uart->RDR & 255);
}

static inline void usb_init(void) {
gpio_init(PIN('A', 11), GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 10); // D+
gpio_init(PIN('A', 12), GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 10); // D-
gpio_init(PIN('A', 9), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 0); // VBUS
gpio_init(PIN('A', 10), GPIO_MODE_AF, GPIO_OTYPE_OPEN_DRAIN, GPIO_SPEED_HIGH,
GPIO_PULL_UP, 10); // ID
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; // Enable USB FS clock
}

static inline void rng_init(void) {
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
RNG->CR |= RNG_CR_RNGEN;
Expand Down
0 examples/stm32/nucleo-f746zg-rndis/link.ld → ...46zg-make-baremetal-builtin-rndis/link.ld
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13 changes: 1 addition & 12 deletions examples/stm32/nucleo-f429zi-rndis/main.c → ...746zg-make-baremetal-builtin-rndis/main.c
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Expand Up @@ -5,7 +5,6 @@
#include "mongoose.h"
#include "tusb.h"

#define LED PIN('B', 7) // On-board LED pin (blue)
static struct mg_tcpip_if *s_ifp;
const uint8_t tud_network_mac_address[6] = {2, 2, 0x84, 0x6A, 0x96, 0};

Expand Down Expand Up @@ -101,17 +100,7 @@ int main(void) {
mg_http_listen(&mgr, "tcp://0.0.0.0:80", fn, &mgr);

MG_INFO(("Init USB ..."));
gpio_init(PIN('A', 11), GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 10); // D+
gpio_init(PIN('A', 12), GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 10); // D-
gpio_init(PIN('A', 9), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 0); // VBUS
gpio_init(PIN('A', 10), GPIO_MODE_AF, GPIO_OTYPE_OPEN_DRAIN, GPIO_SPEED_HIGH,
GPIO_PULL_UP, 10); // ID
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; // Enable USB FS clock
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; // VBUS sensing disable
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // VBUS sensing enable
usb_init();
tusb_init();

MG_INFO(("Init done, starting main loop ..."));
Expand Down
0 ...ples/stm32/nucleo-f746zg-rndis/mongoose.c → ...g-make-baremetal-builtin-rndis/mongoose.c
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0 ...ples/stm32/nucleo-f746zg-rndis/mongoose.h → ...g-make-baremetal-builtin-rndis/mongoose.h
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0 ...tm32/nucleo-f746zg-rndis/netif/ethernet.h → ...-baremetal-builtin-rndis/netif/ethernet.h
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0 ...ples/stm32/nucleo-f746zg-rndis/syscalls.c → ...g-make-baremetal-builtin-rndis/syscalls.c
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0 examples/stm32/nucleo-f746zg-rndis/sysinit.c → ...zg-make-baremetal-builtin-rndis/sysinit.c
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0 ...s/stm32/nucleo-f746zg-rndis/tusb_config.h → ...ake-baremetal-builtin-rndis/tusb_config.h
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0 ...m32/nucleo-f746zg-rndis/usb_descriptors.c → ...baremetal-builtin-rndis/usb_descriptors.c
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3 changes: 0 additions & 3 deletions examples/stm32/nucleo-f746zg-rndis/README.md
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