This processor uses the RV32I instruction set. It runs at up to 40MHz when implemented on a Digilent Arty A7 FPGA Development board.
The lowest level modules were designed using individual logic gates that were replicated with generate loops. The only exceptions to this practice were the Block ROM/RAM that was generated with Xilinx IP, and the 1-bit register that was created with procedural VHDL.
Demonstration of a simple assembly program. The LEDs display a counter that increments when button 0 is pressed, and decrements when button 1 is pressed.
The source code for this program is the file 'counter.asm' under the folder 'Python Scripts'.
Shows the connections between mem_ctl, ram, pc_rom, and the cpu.
Shows the connections between the decoder, alu, program counter, and cpu registers
The Verilog testbenches for segments of the design.
The VHDL design sources for the project.
Handles data transfer between the CPU, RAM, and memory mapped I/O.
Main memory, generated using the Xilinx Block RAM IP.
Instruction memory, generated using the Xilinx Block RAM IP. Set using COE files generated by 'assembler.py'.
The main focus of the project. This module connects the Instruction Decoder, ALU, Program Counter, and CPU Registers.
Contains an adder with an inverter and initial carry bit for subtraction, right barrel shifter, left barrel shifter, comparator, and bitwise AND, OR, and XOR gates.
Determines whether the program needs to branch, and adds either four or an immediate value to either the current instruction address or a stored value.
Identifies the inputs to the ALU and Program Counter, and indicates which functions should be performed.
Reads register addresses from the Instruction Decoder and returns their stored values, and stores data from the ALU or RAM in the given destination register.
Contains Python scripts, their inputs, and their outputs.
A simple assembler that converts pseudo instructions to machine code, simulation inputs, and a coefficient file to load the program in the Xilinx Block ROM.
The demonstration program shown in the video.
A program that was used to test memory mapped I/O and the block RAM.
Generated simulation input to test the instruction ROM.
Generated an assignment statement for the CPU registers that would have taken an annoyingly long time to write by hand.