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Steamin' data, on full-throttle clock.
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Steamin' data, on full-throttle clock.

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  1. openCologne openCologne Public

    Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https:/…

    Verilog 46 3

  2. openXC7-TetriSaraj openXC7-TetriSaraj Public

    Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented…

    Verilog 19 1

  3. openeye-CamSI openeye-CamSI Public

    A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open …

    Verilog 30 6

  4. gtaylormb/opl3_fpga gtaylormb/opl3_fpga Public

    Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

    VHDL 370 43