Clocks can be extracted from GPS satellite signals, or locally generated with MEMS oscillators, SAW resonators, quartz crystal (XTAL, XO) or piezo resonators, often set in “ovens” (TCXO, OCXO), derived from atomic properties (like Cesium Beam, Hydrogen Maser, Rubidium, Strontium or Ytterbium), or obtained in another way.
They differ in Absolute Accuracy, Long-term Frequency Stability (e.g. due to aging), Short-term Frequency Stability (due to temperature changes), Phase Noise (aka Jitter), physical size, complexity, immunity to external interference (due to physical vibrations, humidity, EMP, EW), power consumption, cost, etc. These differences are categorized as “Clock Strata”, whereby a clock source must meet a standardized set of requirements for each Stratum level.
This work is about researching and exploiting the properties of multi-mode crystal oscillators in order to achieve stability comparable to a Stratum 2 Rubidium clock, all at a fraction of the total cost of ownership. We plan on collecting large empirical datasets, constructing experimental prototypes, and using DSP / numerical methods to mitigate (1) temperature variations, (2) dynamic acceleration and (3) static gravity effects. The project aims for XTAL frequency stability by means of numerous mathematical calculations performed in FPGA, using open-source tools, including CflexHDL+PipelineC HLS flow.
This is a Proof-of-Concept (PoC) and stepping stone for future applied research projects on this theme, possibly extending into the field of Artificial Intelligence. In addition to a working prototype (PCBs, FPGA Gateware and Embedded Firmware), the project will deliver a series of scientific papers.
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Physics Package -- Full-custom Analog Board with multi-mode Quartz Crystal
- Design, manufacture and debug the "Physics Package" card.
- Procure and distribute FPGA, ADC and DAC cards.
- Familiarize with ALINX boards.
- Toggle LEDs
- Write RTL for interfaces to ADC and DAC chips
- Write RTL to test their operation
- Perform this testing. Debug and fix the problems as they arise
- Create CPU hardware subsystem based on an open-source RISC-V core, memories, UART and debug port.
- Create a bare-metal software skeleton, as the foundation for writing future DSP applications. Create and test software build flow.
- Test operation of CPU subsystem. Profile its performance.
- Map ADCs and DACs into CPU memory space and test SW communication with them.
- Model quartz crystal and DSP datapath in C or Python.
- Create Theory of Operation document with explanation of concepts, tradeoffs and criteria used to devise solutions.
- Post the Executive Summary here.
- Bring up the complete system with digital and analog card connected to each other.
- Perform manual characterization of individual crystals.
- Develop a semi or fully automated crystal characterization procedure.
- Implement HW side of DSP algorithm on FPGA.
- Implement SW side of DSP algorithm in the RISC-V CPU.
- Integrate DSP hardware and software into a complete system.
- Test the DSP together with crystal.
- we need a reliable reference clock source for this, preferably Stratum 0
- and a good Spectrum Analyzer
- Fine-tune DSP algorithm based on the obtained measurements.
- Conducting additional experiments with the corrected DSP algorithm (in simulation and on hardware).
- Port from Vivado to openXC.
- Develop and test Docker packages with FPGA tools, on a Continuous Integration (CI) system.
- WIP
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We are grateful to NLnet Foundation for their sponsorship of this development activity.
- Soon to come