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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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Repositories

Showing 10 of 107 repositories
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 3 Apache-2.0 1 11 1 Updated Sep 18, 2024
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 65 Apache-2.0 36 66 9 Updated Sep 18, 2024
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 3 Apache-2.0 1 0 0 Updated Sep 18, 2024
  • synlig-logs Public
    chipsalliance/synlig-logs’s past year of commit activity
    0 0 0 0 Updated Sep 18, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 51 Apache-2.0 39 84 51 Updated Sep 18, 2024
  • synlig Public

    SystemVerilog support for Yosys

    chipsalliance/synlig’s past year of commit activity
    Verilog 156 Apache-2.0 20 65 15 Updated Sep 18, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 111 Apache-2.0 21 17 20 Updated Sep 18, 2024
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 243 Apache-2.0 73 20 8 Updated Sep 18, 2024
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible’s past year of commit activity
    C++ 1,323 199 465 (15 issues need help) 22 Updated Sep 18, 2024
  • rocket-uncore Public
    chipsalliance/rocket-uncore’s past year of commit activity
    Scala 4 0 0 1 Updated Sep 18, 2024
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