From 942a4939074b3d0792c5697cb04a531bf55d8e92 Mon Sep 17 00:00:00 2001 From: Christopher Swenson Date: Mon, 9 Dec 2024 16:40:59 -0800 Subject: [PATCH] Add OTP RDL and registers For the OpenTitan fuse (one-time programmable) controller, and also for the related entropy sources. These RDLs is added in the `caliptra-ss` repo at commit: https://github.com/chipsalliance/caliptra-ss/commit/984f22868c978106e8d27928a3eb82a348119396 I also slightly changed the register names to also include their most recent sub-block name so that the digest register names would be less confusing. This caused some changes to the I3C register names (which I've fixed the corresponding code for). --- emulator/app/src/main.rs | 2 + emulator/periph/src/flash_ctrl.rs | 12 +- emulator/periph/src/i3c.rs | 2 +- hw/el2_pic_ctrl.rdl | 4 - hw/entropy_src.rdl | 965 ++++++++++++ hw/flash_ctrl.rdl | 4 - hw/mcu.rdl | 6 + hw/otp_ctrl.rdl | 727 +++++++++ .../generated-emulator/src/entropy_src.rs | 1369 +++++++++++++++++ registers/generated-emulator/src/lib.rs | 2 + registers/generated-emulator/src/otp.rs | 1015 ++++++++++++ registers/generated-emulator/src/root_bus.rs | 53 + .../generated-emulator/src/sha512_acc.rs | 2 +- .../generated-firmware/src/entropy_src.rs | 691 +++++++++ registers/generated-firmware/src/i3c.rs | 236 +-- registers/generated-firmware/src/lib.rs | 2 + registers/generated-firmware/src/otp_ctrl.rs | 250 +++ .../generated-firmware/src/sha512_acc.rs | 38 +- registers/generated-firmware/src/soc_ifc.rs | 74 +- registers/generator/src/codegen.rs | 15 +- runtime/i3c/src/core.rs | 70 +- xtask/src/registers.rs | 26 +- 22 files changed, 5340 insertions(+), 225 deletions(-) create mode 100644 hw/entropy_src.rdl create mode 100644 hw/mcu.rdl create mode 100644 hw/otp_ctrl.rdl create mode 100644 registers/generated-emulator/src/entropy_src.rs create mode 100644 registers/generated-emulator/src/otp.rs create mode 100644 registers/generated-firmware/src/entropy_src.rs create mode 100644 registers/generated-firmware/src/otp_ctrl.rs diff --git a/emulator/app/src/main.rs b/emulator/app/src/main.rs index 89a8714..da0f7b7 100644 --- a/emulator/app/src/main.rs +++ b/emulator/app/src/main.rs @@ -393,6 +393,8 @@ fn run(cli: Emulator, capture_uart_output: bool) -> io::Result> { None, None, None, + None, + None, ); // Set the DMA RAM for the Flash Controller diff --git a/emulator/periph/src/flash_ctrl.rs b/emulator/periph/src/flash_ctrl.rs index f09fd22..7b2fcee 100644 --- a/emulator/periph/src/flash_ctrl.rs +++ b/emulator/periph/src/flash_ctrl.rs @@ -548,7 +548,17 @@ mod test { flash_controller.set_dma_ram(dma_ram); } - AutoRootBus::new(None, None, Some(flash_controller), None, None, None, None) + AutoRootBus::new( + None, + None, + Some(flash_controller), + None, + None, + None, + None, + None, + None, + ) } fn test_helper_prepare_io_page_buffer( diff --git a/emulator/periph/src/i3c.rs b/emulator/periph/src/i3c.rs index c41a3c4..6c92c81 100644 --- a/emulator/periph/src/i3c.rs +++ b/emulator/periph/src/i3c.rs @@ -409,7 +409,7 @@ mod tests { .tcri_send(DynamicI3cAddress::new(8).unwrap(), cmd) .unwrap(); - let mut bus = AutoRootBus::new(None, Some(i3c), None, None, None, None, None); + let mut bus = AutoRootBus::new(None, Some(i3c), None, None, None, None, None, None, None); for _ in 0..10000 { clock.increment_and_process_timer_actions(1, &mut bus); } diff --git a/hw/el2_pic_ctrl.rdl b/hw/el2_pic_ctrl.rdl index 2363619..fd76ef4 100644 --- a/hw/el2_pic_ctrl.rdl +++ b/hw/el2_pic_ctrl.rdl @@ -85,8 +85,4 @@ addrmap el2_pic_ctrl { desc = "Reserved"; } RESERVED[31:0]; } meigwclr[256] @0x00005000; -}; - -addrmap el2_pic { - el2_pic_ctrl el2_pic_ctrl @ 0x6000_0000; }; \ No newline at end of file diff --git a/hw/entropy_src.rdl b/hw/entropy_src.rdl new file mode 100644 index 0000000..200bf5d --- /dev/null +++ b/hw/entropy_src.rdl @@ -0,0 +1,965 @@ +addrmap entropy_src { + reg { + field { + sw = rw; + onwrite = woclr; + desc = "Asserted when entropy source bits are available."; + } ES_ENTROPY_VALID[0:0]; + field { + sw = rw; + onwrite = woclr; + desc = "Asserted when the alert count has been met."; + } ES_HEALTH_TEST_FAILED[1:1]; + field { + sw = rw; + onwrite = woclr; + desc = "Asserted when the observe FIFO has filled to the threshold level."; + } ES_OBSERVE_FIFO_READY[2:2]; + field { + sw = rw; + onwrite = woclr; + desc = "Asserted when a FIFO error occurs, or if an illegal state machine state is reached."; + } ES_FATAL_ERR[3:3]; + } INTERRUPT_STATE @ 0x0; + reg { + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when es_entropy_valid is set."; + } ES_ENTROPY_VALID[0:0]; + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when es_health_test_failed is set."; + } ES_HEALTH_TEST_FAILED[1:1]; + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when es_observe_fifo_ready is set."; + } ES_OBSERVE_FIFO_READY[2:2]; + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when es_fatal_err is set."; + } ES_FATAL_ERR[3:3]; + } INTERRUPT_ENABLE @ 0x4; + reg { + field { + sw = w; + desc = "Write 1 to force es_entropy_valid to 1."; + } ES_ENTROPY_VALID[0:0]; + field { + sw = w; + desc = "Write 1 to force es_health_test_failed to 1."; + } ES_HEALTH_TEST_FAILED[1:1]; + field { + sw = w; + desc = "Write 1 to force es_observe_fifo_ready to 1."; + } ES_OBSERVE_FIFO_READY[2:2]; + field { + sw = w; + desc = "Write 1 to force es_fatal_err to 1."; + } ES_FATAL_ERR[3:3]; + } INTERRUPT_TEST @ 0x8; + reg { + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } RECOV_ALERT[0:0]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_ALERT[1:1]; + } ALERT_TEST @ 0xC; + reg { + field { + desc = "When true, the !!MODULE_ENABLE register can be modified. + When false, it becomes read-only."; + sw = rw; + onwrite = woclr; + } ME_REGWEN[0:0] = 0x1; + } ME_REGWEN @ 0x10; + reg { + field { + desc = "When this bit true and the MODULE_ENABLE field is false, + the REGWEN write enable bit read as true, and is distributed to + all associated control and threshold registers. + When false, these registers become read-only."; + sw = rw; + onwrite = woclr; + } SW_REGUPD[0:0] = 0x1; + } SW_REGUPD @ 0x14; + reg { + field { + desc = "This read-only write enable bit will allow write access + to control and theshold registers that are associated with this bit, + but only when the MODULE_ENABLE field is set to kMultiBitBool4False and the + SW_REGUPD write enable bit is set to true. + When read as false, these registers become read-only."; + sw = r; + } REGWEN[0:0] = 0x1; + } REGWEN @ 0x18; + reg { + field { + desc = "Read of this register shows the ABI of this block."; + sw = r; + } ABI_REVISION[7:0] = 0x3; + field { + desc = "Read of this register shows the revision of this block."; + sw = r; + } HW_REVISION[15:8] = 0x3; + field { + desc = "Read of this register shows the type of chip using this block."; + sw = r; + } CHIP_TYPE[23:16] = 0x1; + } REV @ 0x1C; + reg { + field { + desc = "Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting + this field to kMultiBitBool4False will effectively reset the module. The modules of + the entropy complex may only be enabled and disabled in a specific order, see + Programmers Guide for details."; + sw = rw; + } MODULE_ENABLE[3:0] = 0x9; + } MODULE_ENABLE @ 0x20; + reg { + field { + desc = "Setting this field to kMultiBitBool4True will enable FIPS qualified entropy to be + generated."; + sw = rw; + } FIPS_ENABLE[3:0] = 0x9; + field { + desc = "Setting this field to kMultiBitBool4True will enable reading entropy values from the + ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read + input vector is set to the enable encoding."; + sw = rw; + } ENTROPY_DATA_REG_ENABLE[7:4] = 0x9; + field { + desc = "This field controls the scope (either by-line or by-sum) of the health checks. + If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all + RNG input lines into a single score, and thresholds will be applied to the sum all + the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored + individually. A statistical deviation in any one input line, be it due to + coincidence or failure, will force rejection of the sample, and count toward the + total alert count."; + sw = rw; + } THRESHOLD_SCOPE[15:12] = 0x9; + field { + desc = "Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only + one bit is sampled."; + sw = rw; + } RNG_BIT_ENABLE[23:20] = 0x9; + field { + desc = "When the above bit iset, this field selects which bit from the RNG bus will + be processed when in single RNG bit mode. + This two bit field selects the RNG bit stream: + 0b00: RNG bit 0 + 0b01: RNG bit 1 + 0b10: RNG bit 2 + 0b11: RNG bit 3"; + sw = rw; + } RNG_BIT_SEL[25:24]; + } CONF @ 0x24; + reg { + field { + desc = "Setting this field to kMultiBitBool4True routes the generated entropy value to the ENTROPY_DATA + register to be read by firmware. When this field is kMultiBitBool4False, the generated + entropy will be forwarded out of this module to the hardware interface."; + sw = rw; + } ES_ROUTE[3:0] = 0x9; + field { + desc = "Setting this field to kMultiBitBool4True will bypass the conditioning logic and bring raw entropy + data to the ENTROPY_DATA register. When kMultiBitBool4False, FIPS compliant entropy + will be brought the ENTROPY_DATA register, after being conditioned."; + sw = rw; + } ES_TYPE[7:4] = 0x9; + } ENTROPY_CONTROL @ 0x28; + reg { + field { + desc = "A read of this register provides generated entropy bits to firmware."; + sw = r; + } ENTROPY_DATA[31:0]; + } ENTROPY_DATA @ 0x2C; + reg { + field { + desc = "This is the window size for all health tests. This value is used in normal mode + when entropy is being tested in FIPS/CC compliance mode. + The default value is (2048 bits * 1 clock/4 bits);"; + sw = rw; + } FIPS_WINDOW[15:0] = 0x200; + field { + desc = "This is the window size for all health tests when running in bypass mode. This mode + is active after reset for the first and only test run, or when this mode is + programmed by firmware. + The default value is (384 bits * 1 clock/4 bits); + + Note that currently only a window size of 384 is supported and tested (this + corresponds to the register default value 0x60). Do not use any other values, + unless you know what you are doing."; + sw = rw; + } BYPASS_WINDOW[31:16] = 0x60; + } HEALTH_TEST_WINDOWS @ 0x30; + reg { + field { + desc = "This is the threshold size for the repetition count health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the repetition count health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } REPCNT_THRESHOLDS @ 0x34; + reg { + field { + desc = "This is the threshold size for the repetition count symbol health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the repetition count symbol health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } REPCNTS_THRESHOLDS @ 0x38; + reg { + field { + desc = "This is the threshold size for the adaptive proportion health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the adaptive proportion health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } ADAPTP_HI_THRESHOLDS @ 0x3C; + reg { + field { + desc = "This is the threshold size for the adaptive proportion health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0x0; + field { + desc = "This is the threshold size for the adaptive proportion health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0x0; + } ADAPTP_LO_THRESHOLDS @ 0x40; + reg { + field { + desc = "This is the threshold size for the bucket health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the bucket health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } BUCKET_THRESHOLDS @ 0x44; + reg { + field { + desc = "This is the threshold size for the Markov health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the Markov health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } MARKOV_HI_THRESHOLDS @ 0x48; + reg { + field { + desc = "This is the threshold size for the Markov health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0x0; + field { + desc = "This is the threshold size for the Markov health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0x0; + } MARKOV_LO_THRESHOLDS @ 0x4C; + reg { + field { + desc = "This is the threshold size for the external health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the external health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } EXTHT_HI_THRESHOLDS @ 0x50; + reg { + field { + desc = "This is the threshold size for the external health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0x0; + field { + desc = "This is the threshold size for the external health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0x0; + } EXTHT_LO_THRESHOLDS @ 0x54; + reg { + field { + desc = "High watermark value of the REPCNT test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the REPCNT test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } REPCNT_HI_WATERMARKS @ 0x58; + reg { + field { + desc = "High watermark value of the REPCNTS test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the REPCNTS test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } REPCNTS_HI_WATERMARKS @ 0x5C; + reg { + field { + desc = "High watermark value of the adaptive proportion test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the adaptive proportion test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } ADAPTP_HI_WATERMARKS @ 0x60; + reg { + field { + desc = "Low watermark value of the adaptive proportion test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0] = 0xFFFF; + field { + desc = "Low watermark value of the adaptive proportion test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16] = 0xFFFF; + } ADAPTP_LO_WATERMARKS @ 0x64; + reg { + field { + desc = "High watermark value of the external health test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the external health test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } EXTHT_HI_WATERMARKS @ 0x68; + reg { + field { + desc = "Low watermark value of the external health test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0] = 0xFFFF; + field { + desc = "Low watermark value of the external health test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16] = 0xFFFF; + } EXTHT_LO_WATERMARKS @ 0x6C; + reg { + field { + desc = "High watermark value of the bucket test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the bucket test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } BUCKET_HI_WATERMARKS @ 0x70; + reg { + field { + desc = "High watermark value of the Markov test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the Markov test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } MARKOV_HI_WATERMARKS @ 0x74; + reg { + field { + desc = "Low watermark value of the Markov test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0] = 0xFFFF; + field { + desc = "Low watermark value of the Markov test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16] = 0xFFFF; + } MARKOV_LO_WATERMARKS @ 0x78; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } REPCNT_TOTAL_FAILS[31:0]; + } REPCNT_TOTAL_FAILS @ 0x7C; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } REPCNTS_TOTAL_FAILS[31:0]; + } REPCNTS_TOTAL_FAILS @ 0x80; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } ADAPTP_HI_TOTAL_FAILS[31:0]; + } ADAPTP_HI_TOTAL_FAILS @ 0x84; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } ADAPTP_LO_TOTAL_FAILS[31:0]; + } ADAPTP_LO_TOTAL_FAILS @ 0x88; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } BUCKET_TOTAL_FAILS[31:0]; + } BUCKET_TOTAL_FAILS @ 0x8C; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } MARKOV_HI_TOTAL_FAILS[31:0]; + } MARKOV_HI_TOTAL_FAILS @ 0x90; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } MARKOV_LO_TOTAL_FAILS[31:0]; + } MARKOV_LO_TOTAL_FAILS @ 0x94; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } EXTHT_HI_TOTAL_FAILS[31:0]; + } EXTHT_HI_TOTAL_FAILS @ 0x98; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } EXTHT_LO_TOTAL_FAILS[31:0]; + } EXTHT_LO_TOTAL_FAILS @ 0x9C; + reg { + field { + desc = "This is the threshold size that will signal an alert when + value is reached. A value of zero will disable alerts. + The default value is 2."; + sw = rw; + } ALERT_THRESHOLD[15:0] = 0x2; + field { + desc = "This should be set to the value above, but inverted."; + sw = rw; + } ALERT_THRESHOLD_INV[31:16] = 0xFFFD; + } ALERT_THRESHOLD @ 0xA0; + reg { + field { + desc = "This field will hold a running count of + the total alert count, which is a sum of all of the other + counters in the !!ALERT_FAIL_COUNTS register. + It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } ANY_FAIL_COUNT[15:0]; + } ALERT_SUMMARY_FAIL_COUNTS @ 0xA4; + reg { + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } REPCNT_FAIL_COUNT[7:4]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } ADAPTP_HI_FAIL_COUNT[11:8]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } ADAPTP_LO_FAIL_COUNT[15:12]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } BUCKET_FAIL_COUNT[19:16]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } MARKOV_HI_FAIL_COUNT[23:20]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } MARKOV_LO_FAIL_COUNT[27:24]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } REPCNTS_FAIL_COUNT[31:28]; + } ALERT_FAIL_COUNTS @ 0xA8; + reg { + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } EXTHT_HI_FAIL_COUNT[3:0]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } EXTHT_LO_FAIL_COUNT[7:4]; + } EXTHT_FAIL_COUNTS @ 0xAC; + reg { + field { + desc = "Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. + In this mode, firmware can monitor the post-health test entropy by reading + the observe FIFO. This function also requires that the otp_en_entropy_src_fw_over + input vector is set to the enable encoding."; + sw = rw; + } FW_OV_MODE[3:0] = 0x9; + field { + desc = "Setting this field to kMultiBitBool4True will switch the input into the pre-conditioner + packer FIFO. Firmware can directly write into the packer FIFO, enabling + the ability to insert entropy bits back into the hardware flow. Firmware + can read data from the health check packer FIFO, then do optional health + checks or optional conditioning, then insert the results back into the flow. + Also, the !!FW_OV_CONTROL.FW_OV_MODE bit must be set."; + sw = rw; + } FW_OV_ENTROPY_INSERT[7:4] = 0x9; + } FW_OV_CONTROL @ 0xB0; + reg { + field { + desc = "Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine + to start the SHA3 process and be ready to accept entropy data. This field should + be set prior to writting the FW_OV_WR_DATA register. Once all data has been written, + this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish + processing and push the result into the ESFINAL FIFO. + + Note that clearing this bit to kMultiBitBool4False while there is still unprocessed + entropy in the !!FW_OV_WR_DATA will start the SHA3 engine before data can be added + to the input message, and will also signal a recoverable alert in + !!RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that + !!FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False."; + sw = rw; + } FW_OV_INSERT_START[3:0] = 0x9; + } FW_OV_SHA3_START @ 0xB4; + reg { + field { + desc = "\"When this bit is clear, writes to the FW_OV_WR_DATA register are allowed. + If this bit is set, it is the equivalent to a FIFO full condition, and writes + to the FW_OV_WR_DATA register must be delayed until this bit is reset."; + sw = r; + } FW_OV_WR_FIFO_FULL[0:0]; + } FW_OV_WR_FIFO_FULL @ 0xB8; + reg { + field { + desc = "This bit is set by hardware whenever RNG data is lost due to an overflow condition + in the Observe FIFO. The RNG data rate is slow enough that firmware should always + be able to keep up. This register meanwhile provides an additional check to confirm + that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples. + If an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied."; + sw = r; + } FW_OV_RD_FIFO_OVERFLOW[0:0]; + } FW_OV_RD_FIFO_OVERFLOW @ 0xBC; + reg { + field { + desc = "A read of this register pops and returns the top of the Observe FIFO."; + sw = r; + } FW_OV_RD_DATA[31:0]; + } FW_OV_RD_DATA @ 0xC0; + reg { + field { + desc = "A write to this register will insert entropy back into the entropy source + module flow. Both !!FW_OV_CONTROL.FW_OV_MODE and !!FW_OV_CONTROL.FW_OV_ENTROPY_INSERT bits need to be set + to enable the insertion."; + sw = w; + } FW_OV_WR_DATA[31:0]; + } FW_OV_WR_DATA @ 0xC4; + reg { + field { + desc = "This field will set the threshold that the depth of the Observe FIFO + will be compared with when setting the interrupt status bit. + Note: a value of zero is reserved and not to be used."; + sw = rw; + } OBSERVE_FIFO_THRESH[6:0] = 0x20; + } OBSERVE_FIFO_THRESH @ 0xC8; + reg { + field { + desc = "This field will hold the current depth of the Observe FIFO."; + sw = r; + } OBSERVE_FIFO_DEPTH[6:0]; + } OBSERVE_FIFO_DEPTH @ 0xCC; + reg { + field { + desc = "This is the depth of the entropy source FIFO."; + sw = r; + } ENTROPY_FIFO_DEPTH[2:0]; + field { + desc = "This is the SHA3 finite state machine current state."; + sw = r; + } SHA3_FSM[5:3]; + field { + desc = "This is the SHA3 block processed signal current state."; + sw = r; + } SHA3_BLOCK_PR[6:6]; + field { + desc = "This is the SHA3 squeezing signal current state."; + sw = r; + } SHA3_SQUEEZING[7:7]; + field { + desc = "This is the SHA3 absorbed signal current state."; + sw = r; + } SHA3_ABSORBED[8:8]; + field { + desc = "This is a logic-or of all of the SHA3 error signals."; + sw = r; + } SHA3_ERR[9:9]; + field { + desc = "The entropy_src main state machine is in the idle state."; + sw = r; + } MAIN_SM_IDLE[16:16] = 0x1; + field { + desc = "The entropy_src main state machine is in the boot phase done state."; + sw = r; + } MAIN_SM_BOOT_DONE[17:17]; + } DEBUG_STATUS @ 0xD0; + reg { + field { + desc = "This bit is set when the FIPS_ENABLE field in the !!CONF register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } FIPS_ENABLE_FIELD_ALERT[0:0]; + field { + desc = "This bit is set when the ENTROPY_DATA_REG_ENABLE field in the !!CONF register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ENTROPY_DATA_REG_EN_FIELD_ALERT[1:1]; + field { + desc = "This bit is set when the MODULE_ENABLE field in the !!MODULE_ENABLE register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } MODULE_ENABLE_FIELD_ALERT[2:2]; + field { + desc = "This bit is set when the THRESHOLD_SCOPE field in the !!CONF register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } THRESHOLD_SCOPE_FIELD_ALERT[3:3]; + field { + desc = "This bit is set when the RNG_BIT_ENABLE field in the !!CONF register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } RNG_BIT_ENABLE_FIELD_ALERT[5:5]; + field { + desc = "This bit is set when the FW_OV_SHA3_START field in the !!FW_OV_SHA3_START register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } FW_OV_SHA3_START_FIELD_ALERT[7:7]; + field { + desc = "This bit is set when the FW_OV_MODE field in the !!FW_OV_CONTROL register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } FW_OV_MODE_FIELD_ALERT[8:8]; + field { + desc = "This bit is set when the FW_OV_ENTROPY_INSERT field in the !!FW_OV_CONTROL register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } FW_OV_ENTROPY_INSERT_FIELD_ALERT[9:9]; + field { + desc = "This bit is set when the ES_ROUTE field in the !!ENTROPY_CONTROL register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_ROUTE_FIELD_ALERT[10:10]; + field { + desc = "This bit is set when the ES_TYPE field in the !!ENTROPY_CONTROL register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_TYPE_FIELD_ALERT[11:11]; + field { + desc = "This bit is set when the main state machine detects a threshhold failure state. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_MAIN_SM_ALERT[12:12]; + field { + desc = "This bit is set when the interal entropy bus value is equal to the prior + valid value on the bus, indicating a possible attack. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_BUS_CMP_ALERT[13:13]; + field { + desc = "This bit is set when the !!ALERT_THRESHOLD register is not configured properly. + The upper field must be the exact inverse of the lower field. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_THRESH_CFG_ALERT[14:14]; + field { + desc = "This bit is set when the packer FIFO has been written but was full at the time, + and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes. + This alert would normally be the result of not monitoring the !!FW_OV_WR_FIFO_FULL + register before each write to the !!FW_OV_WR_DATA register. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_FW_OV_WR_ALERT[15:15]; + field { + desc = "This bit is set when !!FW_OV_SHA3_START has been set to MuBi4 False, without + waiting for the FW_OV packer FIFO to clear. The final entropy entry in the FIFO + will not be included in the SHA3 digest. (Rather it will be added to the + subsequent SHA3 digest.) To avoid this alert, monitor !!FW_OV_WR_FIFO_FULL before + clearing !!FW_OV_SHA3_START. This alert only applies when both FW_OV_MODE and + FW_OV_ENTROPY_INSERT are set to MuBi4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_FW_OV_DISABLE_ALERT[16:16]; + } RECOV_ALERT_STS @ 0xD4; + reg { + field { + desc = "This bit will be set to one when an error has been detected for the + esrng FIFO. The type of error is reflected in the type status + bits (bits 28 through 30 of this register). + This bit will stay set until the next reset."; + sw = r; + } SFIFO_ESRNG_ERR[0:0]; + field { + desc = "This bit will be set to one when an error has been detected for the + observe FIFO. The type of error is reflected in the type status + bits (bits 28 through 30 of this register). + This bit will stay set until the next reset."; + sw = r; + } SFIFO_OBSERVE_ERR[1:1]; + field { + desc = "This bit will be set to one when an error has been detected for the + esfinal FIFO. The type of error is reflected in the type status + bits (bits 28 through 30 of this register). + This bit will stay set until the next reset."; + sw = r; + } SFIFO_ESFINAL_ERR[2:2]; + field { + desc = "This bit will be set to one when an illegal state has been detected for the + ES ack stage state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } ES_ACK_SM_ERR[20:20]; + field { + desc = "This bit will be set to one when an illegal state has been detected for the + ES main stage state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } ES_MAIN_SM_ERR[21:21]; + field { + desc = "This bit will be set to one when a hardened counter has detected an error + condition. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } ES_CNTR_ERR[22:22]; + field { + desc = "This bit will be set to one when a SHA3 state error has been detected. + This error will signal a fatal alert, and also an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } SHA3_STATE_ERR[23:23]; + field { + desc = "This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being + active has been detected. + This error will signal a fatal alert, and also an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } SHA3_RST_STORAGE_ERR[24:24]; + field { + desc = "This bit will be set to one when any of the source bits (bits 0 through 1 of this + this register) are asserted as a result of an error pulse generated from + any full FIFO that has been recieved a write pulse. + This bit will stay set until the next reset."; + sw = r; + } FIFO_WRITE_ERR[28:28]; + field { + desc = "This bit will be set to one when any of the source bits (bits 0 through 1 of this + this register) are asserted as a result of an error pulse generated from + any empty FIFO that has recieved a read pulse. + This bit will stay set until the next reset."; + sw = r; + } FIFO_READ_ERR[29:29]; + field { + desc = "This bit will be set to one when any of the source bits (bits 0 through 1 of this + this register) are asserted as a result of an error pulse generated from + any FIFO where both the empty and full status bits are set. + This bit will stay set until the next reset."; + sw = r; + } FIFO_STATE_ERR[30:30]; + } ERR_CODE @ 0xD8; + reg { + field { + desc = "Setting this field will set the bit number for which an error + will be forced in the hardware. This bit number is that same one + found in the !!ERR_CODE register. The action of writing this + register will force an error pulse. The sole purpose of this + register is to test that any error properly propagates to either + an interrupt or an alert."; + sw = rw; + } ERR_CODE_TEST[4:0]; + } ERR_CODE_TEST @ 0xDC; + reg { + field { + desc = "This is the state of the ENTROPY_SRC main state machine. + See the RTL file `entropy_src_main_sm` for the meaning of the values."; + sw = r; + } MAIN_SM_STATE[8:0] = 0xF5; + } MAIN_SM_STATE @ 0xE0; +}; \ No newline at end of file diff --git a/hw/flash_ctrl.rdl b/hw/flash_ctrl.rdl index c5bf6fb..965d1b8 100644 --- a/hw/flash_ctrl.rdl +++ b/hw/flash_ctrl.rdl @@ -76,8 +76,4 @@ addrmap flash_ctrl { } EN[0:0]; } CTRL_REGWEN @ 0x1C; -}; - -addrmap flashctrl_dummy { - flash_ctrl flash_ctrl @ 0x2000_8000; }; \ No newline at end of file diff --git a/hw/mcu.rdl b/hw/mcu.rdl new file mode 100644 index 0000000..65c7a0b --- /dev/null +++ b/hw/mcu.rdl @@ -0,0 +1,6 @@ +addrmap mcu { + el2_pic_ctrl el2_pic_ctrl @ 0x6000_0000; + flash_ctrl flash_ctrl @ 0x2000_8000; + entropy_src entropy_src @ 0x2000_9000; + caliptra_otp_ctrl caliptra_otp_ctrl @ 0x2000_b000; +}; \ No newline at end of file diff --git a/hw/otp_ctrl.rdl b/hw/otp_ctrl.rdl new file mode 100644 index 0000000..b431b6a --- /dev/null +++ b/hw/otp_ctrl.rdl @@ -0,0 +1,727 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +//////////////////////////////////////////////////////////////// +// Fuse Contrller Registers + +//parameter int OtpByteAddrWidth = 12; + +addrmap caliptra_otp_ctrl { + reg { + field { + sw = rw; + onwrite = woclr; + desc = "A direct access command or digest calculation operation has completed."; + } OTP_OPERATION_DONE[0:0]; + field { + sw = rw; + onwrite = woclr; + desc = "An error has occurred in the OTP contrller. Check the !!ERR_CODE register to get more information."; + } OTP_error[1:1]; + } INTERRUPT_STATE @ 0x0; + + reg { + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when otp_operation_done is set."; + } OTP_OPERATION_DONE[0:0]; + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when otp_error is set."; + } OTP_error[1:1]; + } INTERRUPT_ENABLE @ 0x4; + + reg { + field { + sw = w; + desc = "Write 1 to force otp_operation_done to 1."; + } OTP_OPERATION_DONE[0:0]; + field { + sw = w; + desc = "Write 1 to force otp_error to 1."; + } OTP_error[1:1]; + } INTERRUPT_TEST @ 0x8; + + reg { + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_MACr_error[0:0]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_CHECK_error[1:1]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_BUS_INTEG_error[2:2]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_PRIM_OTP_ALERT[3:3]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } RECOV_PRIM_OTP_ALERT[4:4]; + } ALERT_TEST @ 0xC; + + reg { + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } VENDOR_TEST_error[0:0]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } NON_SECRET_FUSES_error[1:1]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } SECRET0_error[2:2]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } SECRET1_error[3:3]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } SECRET2_error[4:4]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } SECRET3_error[5:5]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } LIFE_CYCLE_error[6:6]; + field { + sw = r; + desc = "Set to 1 if an error occurred in the DAI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } DAI_error[7:7]; + field { + sw = r; + desc = "Set to 1 if an error occurred in the LCI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } LCI_error[8:8]; + field { + sw = r; + desc = "Set to 1 if an integrity or consistency check times out.\nThis raises an fatal_check_error alert and is an unrecoverable error condition."; + } TIMEOUT_error[9:9]; + field { + sw = r; + desc = "Set to 1 if the LFSR timer FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition."; + } LFSR_FSM_error[10:10]; + field { + sw = r; + desc = "Set to 1 if the scrambling datapath FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition."; + } SCRAMBLING_FSM_error[11:11]; + field { + sw = r; + desc = "Set to 1 if the key derivation FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition."; + } KEY_DERIV_FSM_error[12:12]; + field { + sw = r; + desc = "This bit is set to 1 if a fatal bus integrity fault is detected.\nThis error triggers a fatal_bus_integ_error alert."; + } BUS_INTEG_error[13:13]; + field { + sw = r; + desc = "Set to 1 if the DAI is idle and ready to accept commands."; + } DAIL_IDLE[14:14]; + field { + sw = r; + desc = "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending."; + } CHECK_PENDING[15:15]; + } STATUS @ 0x10; + + regfile err_code_t { + + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + + name = "error Code Register Block"; + desc = "Set of registers to implement error_code functionality + for Fuse Contrller."; + + default regwidth = 32; // reg property + default accesswidth = 32; // reg property + default sw = r; // field property + default hw = w; // field property + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg err_code_reg_t { + desc = "This register holds information about error conditions that occurred in the agents + interacting with the OTP macr via the internal bus. The error codes should be checked + if the partitions, DAI or LCI flag an error in the !!STATUS register, or when an + !!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error + interrupt, and in addition some errors may trigger either an fatal_macr_error or an + fatal_check_error alert."; + + default sw = r; // field property + default hw = w; // field property + + field { desc = "No error condition has occurred.";} NO_error = 3'h0; + field { desc = "Returned if the OTP macr command was invalid or did not complete successfully + due to a macr malfunction. This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_macr_error alert.";} MACr_error = 3'h1; + field { desc = "A correctable ECC error has occured during an OTP read operation.\nThe corresponding contrller automatically recovers frm this error when\nissuing a new command.";} MACr_ECC_CORR_error = 3'h2; + field { desc = "An uncorrectable ECC error has occurred during an OTP read operation.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present this may be a sign that the device is malfunctioning.\nThis error triggers an fatal_macr_error alert.";} MACr_ECC_UNCORR_error = 3'h3; + field { desc = "This error is returned if a prgramming operation attempted to clear a bit that has previously been prgrammed to 1.\nThe corresponding contrller automatically recovers frm this error when issuing a new command.\n\nNote however that the affected OTP word may be left in an inconsistent state if this error occurs.\nThis can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a backgrund check).\n\nIt is important that SW ensures that each word is only written once, since this can render the device useless.";} MACr_WRITE_BLANK_error = 3'h4; + field { desc = "This error indicates that a locked memory region has been accessed.\nThe corresponding contrller automatically recovers frm this error when issuing a new command.";} ACCESS_error = 3'h5; + field { desc = "An ECC, integrity or consistency mismatch has been detected in the buffer registers.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_check_error alert.";} CHECK_FAIL_error = 3'h6; + field { desc = "The FSM of the corresponding contrller has reached an invalid state, or the FSM has\nbeen moved into a terminal error state due to an escalation action via lc_escalate_en_i.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present, this is a sign that the device has fallen victim to\nan invasive attack. This error triggers an fatal_check_error alert.";} FSM_STATE_error = 3'h7; + }; + + /* ----------- Registers -----------*/ + err_code_reg_t ERR_CODE_0 @0x0; // + err_code_reg_t ERR_CODE_1 @0x4; // + err_code_reg_t ERR_CODE_2 @0x8; // + err_code_reg_t ERR_CODE_3 @0xC; // + err_code_reg_t ERR_CODE_4 @0x10; // + err_code_reg_t ERR_CODE_5 @0x14; // + err_code_reg_t ERR_CODE_6 @0x18; // + err_code_reg_t ERR_CODE_7 @0x1C; // + err_code_reg_t ERR_CODE_8 @0x20; // + /* ---------------------------------*/ + }; + + err_code_t err_code_rf @ 0x14; + + reg { + desc = "Register write enable for all direct access interface registers."; + default sw = rw; + default onwrite = wzc; + default hw = rw; + //default hwext = true; + field { + desc = "This bit contrls whether the DAI registers can be written.\nWrite 0 to it in order to clear the bit.\n\nNote that the hardware also modulates this bit and sets it to 0 temporarily\nduring an OTP operation such that the corresponding address and data registers\ncannot be modified while an operation is pending. The !!DAI_IDLE status bit\nwill also be set to 0 in such a case."; + reset = 0x1; + } REGWEN [0:0]; + } DIRECT_ACCESS_REGWEN @ 0x38; + + reg { + desc = "Command register for direct accesses."; + default sw = w; + default onwrite = wzc; + default hw = r; + //hwext = true; + default reset = 0x0; + default swwe = DIRECT_ACCESS_REGWEN; + field { + desc = "Initiates a readout sequence that reads the location specified\nby !!DIRECT_ACCESS_ADDRESS. The command places the data read into\n!!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions)."; + } RD [0:0]; + field { + desc = "Initiates a prgramming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0\nand !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by\n!!DIRECT_ACCESS_ADDRESS."; + } WR [1:1]; + field { + desc = "Initiates the digest calculation and locking sequence for the partition specified by\n!!DIRECT_ACCESS_ADDRESS."; + } DIGEST [2:2]; + } DIRECT_ACCESS_CMD @ 0x3C; + + reg { + desc = "Address register for direct accesses."; + default sw = rw; + default hw = r; + default reset = 0x0; + default swwe = DIRECT_ACCESS_REGWEN; + field { + desc = "This is the address for the OTP word to be read or written thrugh\nthe direct access interface. Note that the address is aligned to the access size\ninternally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored\nfor 64bit accesses.\n\nFor the digest calculation command, set this register to the partition base offset."; + } ADDRESS [11:0]; + } DIRECT_ACCESS_ADDRESS @ 0x40; + + regfile dir_acc_wdata_t { + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + + name = "Direct Access Wdata Register Block"; + desc = "Set of registers to implement wdata functionality + for Fuse Contrller."; + default reset = 0x0; + default swwe = DIRECT_ACCESS_REGWEN; + default regwidth = 32; // reg property + default accesswidth = 32; // reg property + default sw = r; // field property + default hw = w; // field property + //defalt hwext = true; + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg dai_wdata_t { + desc = "Write data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is being written to."; + + default sw = r; // field prperty + default hw = w; // field prperty + + field { desc = "wdata.";} WDATA [31:0]; + }; + + /* ------------- Registers --------------*/ + dai_wdata_t DIRECT_ACCESS_WDATA_0 @ 0x0; // + dai_wdata_t DIRECT_ACCESS_WDATA_1 @ 0x4; // + /* --------------------------------------*/ + }; + + dir_acc_wdata_t dai_wdata_rf @ 0x44; + + regfile dir_acc_rdata_t { + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + + name = "Direct Access Wdata Register Block"; + desc = "Set of registers to implement wdata functionality + for Fuse Contrller."; + default reset = 0x0; + + default regwidth = 32; // reg prperty + default accesswidth = 32; // reg prperty + default sw = r; // field prperty + default hw = w; // field prperty + //default hwext = true; + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg dai_rdata_t { + desc = "Read data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is read from."; + + default sw = r; // field prperty + default hw = w; // field prperty + + field { desc = "rdata.";} RDATA [31:0]; + }; + + /* ------------- Registers --------------*/ + dai_rdata_t DIRECT_ACCESS_RDATA_0 @ 0x0; // + dai_rdata_t DIRECT_ACCESS_RDATA_1 @ 0x4; // + /* --------------------------------------*/ + }; + + dir_acc_rdata_t dai_rdata_rf @ 0x4C; + + reg { + desc = "Register write enable for !!CHECK_TRIGGER."; + default sw = rw; + default onwrite = wzc; + default hw = na; + field { + desc = "When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore. + Write 0 to clear this bit."; + reset = 0x1; + } REGWEN [0:0]; + } CHECK_TRIGGER_REGWEN @ 0x54; + + reg { + desc = "Command register for direct accesses."; + default sw = w; + default onwrite = woclr; + default hw = r; // Needs to read 0 + //hwext = true; + default reset = 0x0; + default swwe = CHECK_TRIGGER_REGWEN; + field { + desc = "Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts."; + } INTEGRITY[0:0]; + field { + desc = "Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts."; + } CONSISTENCY[1:1]; + } CHECK_TRIGGER @ 0x58; + + reg { + desc = "Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD."; + default sw = w; + default onwrite = wzc; + default hw = na; + field { + desc = "When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore.\nWrite 0 to clear this bit."; + reset = 0x1; + } REGWEN [0:0]; + } CHECK_REGWEN @ 0x5C; + + reg { + desc = "Timeout value for the integrity and consistency checks."; + default sw = rw; + default hw = r; + default swwe = CHECK_REGWEN; + field { + desc = "Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency + check does not complete within the timeout window, an error will be flagged in the !!STATUS register, + an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should + be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the + number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to + rughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the + safe side. A value of zer disables the timeout mechanism (default)."; + reset = 0x0; + } TIMEOUT [31:0]; + } CHECK_TIMEOUT @ 0x60; + + reg { + desc = "This value specifies the maximum period that can be generated pseudo-randomly.\nOnly applies to the HW_CFG* and SECRET* partitions once they are locked."; + default sw = rw; + default hw = r; + default swwe = CHECK_REGWEN; + field { + desc = "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. + A value of zer disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.INTEGRITY."; + reset = 0x0; + } PERIOD [31:0]; + } INTEGRITY_CHECK_PERIOD @ 0x64; + + reg { + desc = "This value specifies the maximum period that can be generated pseudo-randomly.\nThis applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked."; + default sw = rw; + default hw = r; + default swwe = CHECK_REGWEN; + field { + desc = "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz.\nA value of zer disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.CONSISTENCY."; + reset = 0x0; + } PERIOD [31:0]; + } CONSISTENCY_CHECK_PERIOD @ 0x68; + + reg { + desc = "Runtime read lock for the VENDOR_TEST partition."; + default sw = rw; + default onwrite = wzc; + default hw = r; + default swwe = DIRECT_ACCESS_REGWEN; + field { + desc = "When cleared to 0, read access to the VENDOR_TEST partition is locked.\nWrite 0 to clear this bit."; + reset = 0x1; + } READ_LOCK [0:0]; + } VENDOR_TEST_READ_LOCK @ 0x6C; + + reg { + desc = "Runtime read lock for the NON_SECRET_FUSES partition."; + default sw = rw; + default onwrite = wzc; + default hw = r; + default swwe = DIRECT_ACCESS_REGWEN; + field { + desc = "When cleared to 0, read access to the NON_SECRET_FUSES_READ_LOCK partition is locked.\nWrite 0 to clear this bit."; + reset = 0x1; + } READ_LOCK [0:0]; + } NON_SECRET_FUSES_READ_LOCK @ 0x70; + + regfile digest_t { + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + name = "DIGEST"; + desc = "Digest register block"; + default reset = 0x0; + + default sw = r; + default hw = r; + //default hwext = true; + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg digest_reg_t { + name = "DIGEST"; + desc = "Integrity digest for partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the VENDOR_TEST partition is locked and\n the digest becomes visible in this CSR."; + + default sw = r; // field prperty + default hw = w; // field prperty + + field { desc = "Digest.";} DIGEST [31:0]; + }; + + /* ------------- Registers --------------*/ + digest_reg_t DIGEST_0 @ 0x0; // + digest_reg_t DIGEST_1 @ 0x4; // + /* --------------------------------------*/ + }; + + digest_t VENDOR_TEST_DIGEST @ 0x74; + digest_t NON_SECRET_FUSES_DIGEST @ 0x7C; + + regfile secret_digest_t { + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + name = "SECRET_DIGEST"; + desc = "Secret digest register block"; + default reset = 0x0; + + default sw = r; + default hw = r; + //default hwext = true; + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg secret_digest_reg_t { + name = "SECRET_DIGEST"; + desc = "Integrity digest for secret partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked."; + + default sw = r; // field prperty + default hw = w; // field prperty + + field { desc = "Digest.";} DIGEST [31:0]; + }; + + /* ------------- Registers --------------*/ + secret_digest_reg_t DIGEST_0 @ 0x0; // + secret_digest_reg_t DIGEST_1 @ 0x4; // + /* --------------------------------------*/ + }; + + secret_digest_t SECRET0_DIGEST @ 0x84; + secret_digest_t SECRET1_DIGEST @ 0x8C; + secret_digest_t SECRET2_DIGEST @ 0x94; + secret_digest_t SECRET3_DIGEST @ 0x9C; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[0:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field1[1:1] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field2[2:2] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field3[13:4] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field4[26:16] = 0x0; + } CSR0 @ 0xA4; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[6:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field1[7:7] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field2[14:8] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field3[15:15] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field4[31:16] = 0x0; + } CSR1 @ 0xA8; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[0:0] = 0x0; + } CSR2 @ 0xAC; + + reg { + field { + desc = ""; + sw = rw; + hw = rw; + } field0[2:0] = 0x0; + field { + desc = ""; + sw = rw; + onwrite = woclr; + hw = rw; + } field1[13:4] = 0x0; + field { + desc = ""; + sw = rw; + onwrite = woclr; + hw = rw; + } field2[16:16] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field3[17:17] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field4[18:18] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field5[19:19] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field6[20:20] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field7[21:21] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field8[22:22] = 0x0; + } CSR3 @ 0xB0; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[9:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field1[12:12] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field2[13:13] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field3[14:14] = 0x0; + } CSR4 @ 0xB4; + + reg { + field { + desc = ""; + sw = rw; + hw = rw; + } field0[5:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field1[7:6] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field2[8] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field3[11:9] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field4[12] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field5[13] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field6[31:16] = 0x0; + } CSR5 @ 0xB8; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[9:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field1[11:11] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field2[12:12] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field3[31:16] = 0x0; + } CSR6 @ 0xBC; + + reg { + field { + desc = ""; + sw = r; + hw = rw; + } field0[5:0] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field1[10:8] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field2[14:14] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field3[15:15] = 0x0; + } CSR7 @ 0xC0; +}; \ No newline at end of file diff --git a/registers/generated-emulator/src/entropy_src.rs b/registers/generated-emulator/src/entropy_src.rs new file mode 100644 index 0000000..9d0f5f1 --- /dev/null +++ b/registers/generated-emulator/src/entropy_src.rs @@ -0,0 +1,1369 @@ +// Licensed under the Apache-2.0 license. +// +// generated by registers_generator with caliptra-ss repo at a621fff9df7015821eda6f7f73265fef74a01375 +// +#[allow(unused_imports)] +use tock_registers::interfaces::{Readable, Writeable}; +pub trait EntropySrcPeripheral { + fn poll(&mut self) {} + fn warm_reset(&mut self) {} + fn update_reset(&mut self) {} + fn read_interrupt_state( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::InterruptState::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_interrupt_state( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::InterruptState::Register, + >, + ) { + } + fn read_entropy_interrupt_enable( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::EntropyInterruptEnable::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_entropy_interrupt_enable( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::EntropyInterruptEnable::Register, + >, + ) { + } + fn write_interrupt_test( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::InterruptTest::Register, + >, + ) { + } + fn write_alert_test( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::AlertTest::Register, + >, + ) { + } + fn read_me_regwen( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MeRegwen::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_me_regwen( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MeRegwen::Register, + >, + ) { + } + fn read_sw_regupd( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::SwRegupd::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_sw_regupd( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::SwRegupd::Register, + >, + ) { + } + fn read_regwen( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::Regwen::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_rev( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_module_enable( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ModuleEnable::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_module_enable( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ModuleEnable::Register, + >, + ) { + } + fn read_conf( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_conf( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::Conf::Register, + >, + ) { + } + fn read_entropy_control( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::EntropyControl::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_entropy_control( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::EntropyControl::Register, + >, + ) { + } + fn read_entropy_data(&mut self, _size: emulator_types::RvSize) -> emulator_types::RvData { + 0 + } + fn read_health_test_windows( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::HealthTestWindows::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_health_test_windows( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::HealthTestWindows::Register, + >, + ) { + } + fn read_repcnt_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::RepcntThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_repcnt_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::RepcntThresholds::Register, + >, + ) { + } + fn read_repcnts_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::RepcntsThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_repcnts_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::RepcntsThresholds::Register, + >, + ) { + } + fn read_adaptp_hi_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AdaptpHiThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_adaptp_hi_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AdaptpHiThresholds::Register, + >, + ) { + } + fn read_adaptp_lo_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AdaptpLoThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_adaptp_lo_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AdaptpLoThresholds::Register, + >, + ) { + } + fn read_bucket_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::BucketThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_bucket_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::BucketThresholds::Register, + >, + ) { + } + fn read_markov_hi_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MarkovHiThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_markov_hi_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MarkovHiThresholds::Register, + >, + ) { + } + fn read_markov_lo_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MarkovLoThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_markov_lo_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MarkovLoThresholds::Register, + >, + ) { + } + fn read_extht_hi_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ExthtHiThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_extht_hi_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ExthtHiThresholds::Register, + >, + ) { + } + fn read_extht_lo_thresholds( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ExthtLoThresholds::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_extht_lo_thresholds( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ExthtLoThresholds::Register, + >, + ) { + } + fn read_repcnt_hi_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::RepcntHiWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_repcnts_hi_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::RepcntsHiWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_adaptp_hi_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AdaptpHiWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_adaptp_lo_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AdaptpLoWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_extht_hi_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ExthtHiWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_extht_lo_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ExthtLoWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_bucket_hi_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::BucketHiWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_markov_hi_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MarkovHiWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_markov_lo_watermarks( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MarkovLoWatermarks::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_repcnt_total_fails(&mut self, _size: emulator_types::RvSize) -> emulator_types::RvData { + 0 + } + fn read_repcnts_total_fails( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_adaptp_hi_total_fails( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_adaptp_lo_total_fails( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_bucket_total_fails(&mut self, _size: emulator_types::RvSize) -> emulator_types::RvData { + 0 + } + fn read_markov_hi_total_fails( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_markov_lo_total_fails( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_extht_hi_total_fails( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_extht_lo_total_fails( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_alert_threshold( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AlertThreshold::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_alert_threshold( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AlertThreshold::Register, + >, + ) { + } + fn read_alert_summary_fail_counts( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AlertSummaryFailCounts::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_alert_fail_counts( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::AlertFailCounts::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_extht_fail_counts( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ExthtFailCounts::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_fw_ov_control( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::FwOvControl::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_fw_ov_control( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::FwOvControl::Register, + >, + ) { + } + fn read_fw_ov_sha3_start( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::FwOvSha3Start::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_fw_ov_sha3_start( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::FwOvSha3Start::Register, + >, + ) { + } + fn read_fw_ov_wr_fifo_full( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::FwOvWrFifoFull::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_fw_ov_rd_fifo_overflow( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::FwOvRdFifoOverflow::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_fw_ov_rd_data(&mut self, _size: emulator_types::RvSize) -> emulator_types::RvData { + 0 + } + fn write_fw_ov_wr_data(&mut self, _size: emulator_types::RvSize, _val: emulator_types::RvData) { + } + fn read_observe_fifo_thresh( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ObserveFifoThresh::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_observe_fifo_thresh( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ObserveFifoThresh::Register, + >, + ) { + } + fn read_observe_fifo_depth( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ObserveFifoDepth::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_debug_status( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::DebugStatus::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_recov_alert_sts( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::RecovAlertSts::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_recov_alert_sts( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::RecovAlertSts::Register, + >, + ) { + } + fn read_err_code( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ErrCode::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_test( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ErrCodeTest::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_err_code_test( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::ErrCodeTest::Register, + >, + ) { + } + fn read_main_sm_state( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::entropy_src::bits::MainSmState::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } +} +pub struct EntropySrcBus { + pub periph: Box, +} +impl emulator_bus::Bus for EntropySrcBus { + fn read( + &mut self, + size: emulator_types::RvSize, + addr: emulator_types::RvAddr, + ) -> Result { + match (size, addr) { + (emulator_types::RvSize::Word, 0) => Ok(emulator_types::RvData::from( + self.periph + .read_interrupt_state(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 1..=3) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 4) => Ok(emulator_types::RvData::from( + self.periph + .read_entropy_interrupt_enable(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 5..=7) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x10) => Ok(emulator_types::RvData::from( + self.periph + .read_me_regwen(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x11..=0x13) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x14) => Ok(emulator_types::RvData::from( + self.periph + .read_sw_regupd(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x15..=0x17) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x18) => Ok(emulator_types::RvData::from( + self.periph + .read_regwen(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x19..=0x1b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x1c) => Ok(emulator_types::RvData::from( + self.periph.read_rev(emulator_types::RvSize::Word).reg.get(), + )), + (emulator_types::RvSize::Word, 0x1d..=0x1f) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x20) => Ok(emulator_types::RvData::from( + self.periph + .read_module_enable(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x21..=0x23) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x24) => Ok(emulator_types::RvData::from( + self.periph + .read_conf(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x25..=0x27) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x28) => Ok(emulator_types::RvData::from( + self.periph + .read_entropy_control(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x29..=0x2b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (size, 0x2c) => Ok(self.periph.read_entropy_data(size)), + (_, 0x2d..=0x2f) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (emulator_types::RvSize::Word, 0x30) => Ok(emulator_types::RvData::from( + self.periph + .read_health_test_windows(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x31..=0x33) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x34) => Ok(emulator_types::RvData::from( + self.periph + .read_repcnt_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x35..=0x37) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x38) => Ok(emulator_types::RvData::from( + self.periph + .read_repcnts_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x39..=0x3b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x3c) => Ok(emulator_types::RvData::from( + self.periph + .read_adaptp_hi_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x3d..=0x3f) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x40) => Ok(emulator_types::RvData::from( + self.periph + .read_adaptp_lo_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x41..=0x43) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x44) => Ok(emulator_types::RvData::from( + self.periph + .read_bucket_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x45..=0x47) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x48) => Ok(emulator_types::RvData::from( + self.periph + .read_markov_hi_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x49..=0x4b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x4c) => Ok(emulator_types::RvData::from( + self.periph + .read_markov_lo_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x4d..=0x4f) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x50) => Ok(emulator_types::RvData::from( + self.periph + .read_extht_hi_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x51..=0x53) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x54) => Ok(emulator_types::RvData::from( + self.periph + .read_extht_lo_thresholds(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x55..=0x57) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x58) => Ok(emulator_types::RvData::from( + self.periph + .read_repcnt_hi_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x59..=0x5b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x5c) => Ok(emulator_types::RvData::from( + self.periph + .read_repcnts_hi_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x5d..=0x5f) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x60) => Ok(emulator_types::RvData::from( + self.periph + .read_adaptp_hi_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x61..=0x63) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x64) => Ok(emulator_types::RvData::from( + self.periph + .read_adaptp_lo_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x65..=0x67) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x68) => Ok(emulator_types::RvData::from( + self.periph + .read_extht_hi_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x69..=0x6b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x6c) => Ok(emulator_types::RvData::from( + self.periph + .read_extht_lo_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x6d..=0x6f) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x70) => Ok(emulator_types::RvData::from( + self.periph + .read_bucket_hi_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x71..=0x73) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x74) => Ok(emulator_types::RvData::from( + self.periph + .read_markov_hi_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x75..=0x77) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x78) => Ok(emulator_types::RvData::from( + self.periph + .read_markov_lo_watermarks(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x79..=0x7b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (size, 0x7c) => Ok(self.periph.read_repcnt_total_fails(size)), + (_, 0x7d..=0x7f) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x80) => Ok(self.periph.read_repcnts_total_fails(size)), + (_, 0x81..=0x83) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x84) => Ok(self.periph.read_adaptp_hi_total_fails(size)), + (_, 0x85..=0x87) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x88) => Ok(self.periph.read_adaptp_lo_total_fails(size)), + (_, 0x89..=0x8b) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x8c) => Ok(self.periph.read_bucket_total_fails(size)), + (_, 0x8d..=0x8f) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x90) => Ok(self.periph.read_markov_hi_total_fails(size)), + (_, 0x91..=0x93) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x94) => Ok(self.periph.read_markov_lo_total_fails(size)), + (_, 0x95..=0x97) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x98) => Ok(self.periph.read_extht_hi_total_fails(size)), + (_, 0x99..=0x9b) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x9c) => Ok(self.periph.read_extht_lo_total_fails(size)), + (_, 0x9d..=0x9f) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (emulator_types::RvSize::Word, 0xa0) => Ok(emulator_types::RvData::from( + self.periph + .read_alert_threshold(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xa1..=0xa3) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xa4) => Ok(emulator_types::RvData::from( + self.periph + .read_alert_summary_fail_counts(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xa5..=0xa7) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xa8) => Ok(emulator_types::RvData::from( + self.periph + .read_alert_fail_counts(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xa9..=0xab) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xac) => Ok(emulator_types::RvData::from( + self.periph + .read_extht_fail_counts(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xad..=0xaf) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb0) => Ok(emulator_types::RvData::from( + self.periph + .read_fw_ov_control(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xb1..=0xb3) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb4) => Ok(emulator_types::RvData::from( + self.periph + .read_fw_ov_sha3_start(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xb5..=0xb7) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb8) => Ok(emulator_types::RvData::from( + self.periph + .read_fw_ov_wr_fifo_full(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xb9..=0xbb) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xbc) => Ok(emulator_types::RvData::from( + self.periph + .read_fw_ov_rd_fifo_overflow(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xbd..=0xbf) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (size, 0xc0) => Ok(self.periph.read_fw_ov_rd_data(size)), + (_, 0xc1..=0xc3) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (emulator_types::RvSize::Word, 0xc8) => Ok(emulator_types::RvData::from( + self.periph + .read_observe_fifo_thresh(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xc9..=0xcb) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xcc) => Ok(emulator_types::RvData::from( + self.periph + .read_observe_fifo_depth(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xcd..=0xcf) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xd0) => Ok(emulator_types::RvData::from( + self.periph + .read_debug_status(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xd1..=0xd3) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xd4) => Ok(emulator_types::RvData::from( + self.periph + .read_recov_alert_sts(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xd5..=0xd7) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xd8) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xd9..=0xdb) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xdc) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_test(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xdd..=0xdf) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xe0) => Ok(emulator_types::RvData::from( + self.periph + .read_main_sm_state(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xe1..=0xe3) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + _ => Err(emulator_bus::BusError::LoadAccessFault), + } + } + fn write( + &mut self, + size: emulator_types::RvSize, + addr: emulator_types::RvAddr, + val: emulator_types::RvData, + ) -> Result<(), emulator_bus::BusError> { + match (size, addr) { + (emulator_types::RvSize::Word, 0) => { + self.periph.write_interrupt_state( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 1..=3) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 4) => { + self.periph.write_entropy_interrupt_enable( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 5..=7) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 8) => { + self.periph.write_interrupt_test( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 9..=0xb) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xc) => { + self.periph.write_alert_test( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xd..=0xf) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x10) => { + self.periph.write_me_regwen( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x11..=0x13) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x14) => { + self.periph.write_sw_regupd( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x15..=0x17) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x20) => { + self.periph.write_module_enable( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x21..=0x23) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x24) => { + self.periph.write_conf( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x25..=0x27) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x28) => { + self.periph.write_entropy_control( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x29..=0x2b) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x30) => { + self.periph.write_health_test_windows( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x31..=0x33) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x34) => { + self.periph.write_repcnt_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x35..=0x37) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x38) => { + self.periph.write_repcnts_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x39..=0x3b) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x3c) => { + self.periph.write_adaptp_hi_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x3d..=0x3f) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x40) => { + self.periph.write_adaptp_lo_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x41..=0x43) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x44) => { + self.periph.write_bucket_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x45..=0x47) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x48) => { + self.periph.write_markov_hi_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x49..=0x4b) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x4c) => { + self.periph.write_markov_lo_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x4d..=0x4f) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x50) => { + self.periph.write_extht_hi_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x51..=0x53) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x54) => { + self.periph.write_extht_lo_thresholds( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x55..=0x57) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xa0) => { + self.periph.write_alert_threshold( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xa1..=0xa3) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb0) => { + self.periph.write_fw_ov_control( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xb1..=0xb3) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb4) => { + self.periph.write_fw_ov_sha3_start( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xb5..=0xb7) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (size, 0xc4) => { + self.periph.write_fw_ov_wr_data(size, val); + Ok(()) + } + (_, 0xc5..=0xc7) => Err(emulator_bus::BusError::StoreAddrMisaligned), + (emulator_types::RvSize::Word, 0xc8) => { + self.periph.write_observe_fifo_thresh( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xc9..=0xcb) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xd4) => { + self.periph.write_recov_alert_sts( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xd5..=0xd7) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xdc) => { + self.periph.write_err_code_test( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xdd..=0xdf) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + _ => Err(emulator_bus::BusError::StoreAccessFault), + } + } + fn poll(&mut self) { + self.periph.poll(); + } + fn warm_reset(&mut self) { + self.periph.warm_reset(); + } + fn update_reset(&mut self) { + self.periph.update_reset(); + } +} diff --git a/registers/generated-emulator/src/lib.rs b/registers/generated-emulator/src/lib.rs index b75c079..0198043 100644 --- a/registers/generated-emulator/src/lib.rs +++ b/registers/generated-emulator/src/lib.rs @@ -3,9 +3,11 @@ // generated by registers_generator with caliptra-ss repo at a621fff9df7015821eda6f7f73265fef74a01375 // pub mod el2_pic; +pub mod entropy_src; pub mod flash; pub mod i3c; pub mod mbox; +pub mod otp; pub mod root_bus; pub mod sha512_acc; pub mod soc; diff --git a/registers/generated-emulator/src/otp.rs b/registers/generated-emulator/src/otp.rs new file mode 100644 index 0000000..4fdfffb --- /dev/null +++ b/registers/generated-emulator/src/otp.rs @@ -0,0 +1,1015 @@ +// Licensed under the Apache-2.0 license. +// +// generated by registers_generator with caliptra-ss repo at a621fff9df7015821eda6f7f73265fef74a01375 +// +#[allow(unused_imports)] +use tock_registers::interfaces::{Readable, Writeable}; +pub trait OtpPeripheral { + fn poll(&mut self) {} + fn warm_reset(&mut self) {} + fn update_reset(&mut self) {} + fn read_interrupt_state( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::InterruptState::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_interrupt_state( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::InterruptState::Register, + >, + ) { + } + fn read_interrupt_enable( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::i3c::bits::InterruptEnable::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_interrupt_enable( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::i3c::bits::InterruptEnable::Register, + >, + ) { + } + fn write_interrupt_test( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::InterruptTest::Register, + >, + ) { + } + fn write_alert_test( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::AlertTest::Register, + >, + ) { + } + fn read_status( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_direct_access_regwen( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::DirectAccessRegwen::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_direct_access_regwen( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::DirectAccessRegwen::Register, + >, + ) { + } + fn write_direct_access_cmd( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::DirectAccessCmd::Register, + >, + ) { + } + fn read_direct_access_address( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::DirectAccessAddress::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_direct_access_address( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::DirectAccessAddress::Register, + >, + ) { + } + fn read_check_trigger_regwen( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::CheckTriggerRegwen::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_check_trigger_regwen( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::CheckTriggerRegwen::Register, + >, + ) { + } + fn write_check_trigger( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::CheckTrigger::Register, + >, + ) { + } + fn write_check_regwen( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::CheckRegwen::Register, + >, + ) { + } + fn read_check_timeout(&mut self, _size: emulator_types::RvSize) -> emulator_types::RvData { + 0 + } + fn write_check_timeout(&mut self, _size: emulator_types::RvSize, _val: emulator_types::RvData) { + } + fn read_integrity_check_period( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn write_integrity_check_period( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_types::RvData, + ) { + } + fn read_consistency_check_period( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn write_consistency_check_period( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_types::RvData, + ) { + } + fn read_vendor_test_read_lock( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::VendorTestReadLock::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_vendor_test_read_lock( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::VendorTestReadLock::Register, + >, + ) { + } + fn read_non_secret_fuses_read_lock( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::NonSecretFusesReadLock::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_non_secret_fuses_read_lock( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::NonSecretFusesReadLock::Register, + >, + ) { + } + fn read_csr0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_csr0( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::Csr0::Register, + >, + ) { + } + fn read_csr1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_csr1( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::Csr1::Register, + >, + ) { + } + fn read_csr2( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_csr2( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::Csr2::Register, + >, + ) { + } + fn read_csr3( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_csr3( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::Csr3::Register, + >, + ) { + } + fn read_csr4( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_csr4( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::Csr4::Register, + >, + ) { + } + fn read_csr5( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_csr5( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::Csr5::Register, + >, + ) { + } + fn read_csr6( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn write_csr6( + &mut self, + _size: emulator_types::RvSize, + _val: emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::Csr6::Register, + >, + ) { + } + fn read_csr7( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister + { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_2( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_3( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_4( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_5( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_6( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_7( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_err_code_rf_err_code_8( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_bus::ReadWriteRegister< + u32, + registers_generated::otp_ctrl::bits::ErrCodeRegT::Register, + > { + emulator_bus::ReadWriteRegister::new(0) + } + fn read_dai_wdata_rf_direct_access_wdata_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_dai_wdata_rf_direct_access_wdata_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_dai_rdata_rf_direct_access_rdata_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_dai_rdata_rf_direct_access_rdata_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_vendor_test_digest_digest_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_vendor_test_digest_digest_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_non_secret_fuses_digest_digest_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_non_secret_fuses_digest_digest_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_secret0_digest_digest_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_secret0_digest_digest_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_secret1_digest_digest_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_secret1_digest_digest_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_secret2_digest_digest_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_secret2_digest_digest_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_secret3_digest_digest_0( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } + fn read_secret3_digest_digest_1( + &mut self, + _size: emulator_types::RvSize, + ) -> emulator_types::RvData { + 0 + } +} +pub struct OtpBus { + pub periph: Box, +} +impl emulator_bus::Bus for OtpBus { + fn read( + &mut self, + size: emulator_types::RvSize, + addr: emulator_types::RvAddr, + ) -> Result { + match (size, addr) { + (emulator_types::RvSize::Word, 0) => Ok(emulator_types::RvData::from( + self.periph + .read_interrupt_state(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 1..=3) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 4) => Ok(emulator_types::RvData::from( + self.periph + .read_interrupt_enable(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 5..=7) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x10) => Ok(emulator_types::RvData::from( + self.periph + .read_status(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x11..=0x13) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x38) => Ok(emulator_types::RvData::from( + self.periph + .read_direct_access_regwen(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x39..=0x3b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x40) => Ok(emulator_types::RvData::from( + self.periph + .read_direct_access_address(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x41..=0x43) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x54) => Ok(emulator_types::RvData::from( + self.periph + .read_check_trigger_regwen(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x55..=0x57) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (size, 0x60) => Ok(self.periph.read_check_timeout(size)), + (_, 0x61..=0x63) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x64) => Ok(self.periph.read_integrity_check_period(size)), + (_, 0x65..=0x67) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x68) => Ok(self.periph.read_consistency_check_period(size)), + (_, 0x69..=0x6b) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (emulator_types::RvSize::Word, 0x6c) => Ok(emulator_types::RvData::from( + self.periph + .read_vendor_test_read_lock(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x6d..=0x6f) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x70) => Ok(emulator_types::RvData::from( + self.periph + .read_non_secret_fuses_read_lock(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x71..=0x73) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xa4) => Ok(emulator_types::RvData::from( + self.periph + .read_csr0(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xa5..=0xa7) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xa8) => Ok(emulator_types::RvData::from( + self.periph + .read_csr1(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xa9..=0xab) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xac) => Ok(emulator_types::RvData::from( + self.periph + .read_csr2(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xad..=0xaf) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb0) => Ok(emulator_types::RvData::from( + self.periph + .read_csr3(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xb1..=0xb3) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb4) => Ok(emulator_types::RvData::from( + self.periph + .read_csr4(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xb5..=0xb7) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb8) => Ok(emulator_types::RvData::from( + self.periph + .read_csr5(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xb9..=0xbb) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xbc) => Ok(emulator_types::RvData::from( + self.periph + .read_csr6(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xbd..=0xbf) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xc0) => Ok(emulator_types::RvData::from( + self.periph + .read_csr7(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0xc1..=0xc3) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x14) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_0(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x15..=0x17) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x18) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_1(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x19..=0x1b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x1c) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_2(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x1d..=0x1f) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x20) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_3(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x21..=0x23) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x24) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_4(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x25..=0x27) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x28) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_5(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x29..=0x2b) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x2c) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_6(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x2d..=0x2f) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x30) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_7(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x31..=0x33) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x34) => Ok(emulator_types::RvData::from( + self.periph + .read_err_code_rf_err_code_8(emulator_types::RvSize::Word) + .reg + .get(), + )), + (emulator_types::RvSize::Word, 0x35..=0x37) => { + Err(emulator_bus::BusError::LoadAddrMisaligned) + } + (size, 0x44) => Ok(self.periph.read_dai_wdata_rf_direct_access_wdata_0(size)), + (_, 0x45..=0x47) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x48) => Ok(self.periph.read_dai_wdata_rf_direct_access_wdata_1(size)), + (_, 0x49..=0x4b) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x4c) => Ok(self.periph.read_dai_rdata_rf_direct_access_rdata_0(size)), + (_, 0x4d..=0x4f) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x50) => Ok(self.periph.read_dai_rdata_rf_direct_access_rdata_1(size)), + (_, 0x51..=0x53) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x74) => Ok(self.periph.read_vendor_test_digest_digest_0(size)), + (_, 0x75..=0x77) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x78) => Ok(self.periph.read_vendor_test_digest_digest_1(size)), + (_, 0x79..=0x7b) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x7c) => Ok(self.periph.read_non_secret_fuses_digest_digest_0(size)), + (_, 0x7d..=0x7f) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x80) => Ok(self.periph.read_non_secret_fuses_digest_digest_1(size)), + (_, 0x81..=0x83) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x84) => Ok(self.periph.read_secret0_digest_digest_0(size)), + (_, 0x85..=0x87) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x88) => Ok(self.periph.read_secret0_digest_digest_1(size)), + (_, 0x89..=0x8b) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x8c) => Ok(self.periph.read_secret1_digest_digest_0(size)), + (_, 0x8d..=0x8f) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x90) => Ok(self.periph.read_secret1_digest_digest_1(size)), + (_, 0x91..=0x93) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x94) => Ok(self.periph.read_secret2_digest_digest_0(size)), + (_, 0x95..=0x97) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x98) => Ok(self.periph.read_secret2_digest_digest_1(size)), + (_, 0x99..=0x9b) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0x9c) => Ok(self.periph.read_secret3_digest_digest_0(size)), + (_, 0x9d..=0x9f) => Err(emulator_bus::BusError::LoadAddrMisaligned), + (size, 0xa0) => Ok(self.periph.read_secret3_digest_digest_1(size)), + (_, 0xa1..=0xa3) => Err(emulator_bus::BusError::LoadAddrMisaligned), + _ => Err(emulator_bus::BusError::LoadAccessFault), + } + } + fn write( + &mut self, + size: emulator_types::RvSize, + addr: emulator_types::RvAddr, + val: emulator_types::RvData, + ) -> Result<(), emulator_bus::BusError> { + match (size, addr) { + (emulator_types::RvSize::Word, 0) => { + self.periph.write_interrupt_state( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 1..=3) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 4) => { + self.periph.write_interrupt_enable( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 5..=7) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 8) => { + self.periph.write_interrupt_test( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 9..=0xb) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xc) => { + self.periph.write_alert_test( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xd..=0xf) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x38) => { + self.periph.write_direct_access_regwen( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x39..=0x3b) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x3c) => { + self.periph.write_direct_access_cmd( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x3d..=0x3f) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x40) => { + self.periph.write_direct_access_address( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x41..=0x43) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x54) => { + self.periph.write_check_trigger_regwen( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x55..=0x57) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x58) => { + self.periph.write_check_trigger( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x59..=0x5b) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x5c) => { + self.periph.write_check_regwen( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x5d..=0x5f) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (size, 0x60) => { + self.periph.write_check_timeout(size, val); + Ok(()) + } + (_, 0x61..=0x63) => Err(emulator_bus::BusError::StoreAddrMisaligned), + (size, 0x64) => { + self.periph.write_integrity_check_period(size, val); + Ok(()) + } + (_, 0x65..=0x67) => Err(emulator_bus::BusError::StoreAddrMisaligned), + (size, 0x68) => { + self.periph.write_consistency_check_period(size, val); + Ok(()) + } + (_, 0x69..=0x6b) => Err(emulator_bus::BusError::StoreAddrMisaligned), + (emulator_types::RvSize::Word, 0x6c) => { + self.periph.write_vendor_test_read_lock( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x6d..=0x6f) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0x70) => { + self.periph.write_non_secret_fuses_read_lock( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0x71..=0x73) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xa4) => { + self.periph.write_csr0( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xa5..=0xa7) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xa8) => { + self.periph.write_csr1( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xa9..=0xab) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xac) => { + self.periph.write_csr2( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xad..=0xaf) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb0) => { + self.periph.write_csr3( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xb1..=0xb3) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb4) => { + self.periph.write_csr4( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xb5..=0xb7) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xb8) => { + self.periph.write_csr5( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xb9..=0xbb) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + (emulator_types::RvSize::Word, 0xbc) => { + self.periph.write_csr6( + emulator_types::RvSize::Word, + emulator_bus::ReadWriteRegister::new(val), + ); + Ok(()) + } + (emulator_types::RvSize::Word, 0xbd..=0xbf) => { + Err(emulator_bus::BusError::StoreAddrMisaligned) + } + _ => Err(emulator_bus::BusError::StoreAccessFault), + } + } + fn poll(&mut self) { + self.periph.poll(); + } + fn warm_reset(&mut self) { + self.periph.warm_reset(); + } + fn update_reset(&mut self) { + self.periph.update_reset(); + } +} diff --git a/registers/generated-emulator/src/root_bus.rs b/registers/generated-emulator/src/root_bus.rs index 693ce98..6b1b6b9 100644 --- a/registers/generated-emulator/src/root_bus.rs +++ b/registers/generated-emulator/src/root_bus.rs @@ -6,6 +6,8 @@ pub struct AutoRootBus { delegate: Option>, pub i3c_periph: Option, pub flash_periph: Option, + pub entropy_src_periph: Option, + pub otp_periph: Option, pub mbox_periph: Option, pub sha512_acc_periph: Option, pub soc_periph: Option, @@ -17,6 +19,8 @@ impl AutoRootBus { delegate: Option>, i3c_periph: Option>, flash_periph: Option>, + entropy_src_periph: Option>, + otp_periph: Option>, mbox_periph: Option>, sha512_acc_periph: Option>, soc_periph: Option>, @@ -26,6 +30,9 @@ impl AutoRootBus { delegate, i3c_periph: i3c_periph.map(|p| crate::i3c::I3cBus { periph: p }), flash_periph: flash_periph.map(|p| crate::flash::FlashBus { periph: p }), + entropy_src_periph: entropy_src_periph + .map(|p| crate::entropy_src::EntropySrcBus { periph: p }), + otp_periph: otp_periph.map(|p| crate::otp::OtpBus { periph: p }), mbox_periph: mbox_periph.map(|p| crate::mbox::MboxBus { periph: p }), sha512_acc_periph: sha512_acc_periph .map(|p| crate::sha512_acc::Sha512AccBus { periph: p }), @@ -55,6 +62,20 @@ impl emulator_bus::Bus for AutoRootBus { Err(emulator_bus::BusError::LoadAccessFault) } } + 0x2000_9000..=0x2000_a9d4 => { + if let Some(periph) = self.entropy_src_periph.as_mut() { + periph.read(size, addr - 0x2000_9000) + } else { + Err(emulator_bus::BusError::LoadAccessFault) + } + } + 0x2000_b000..=0x2000_b9dc => { + if let Some(periph) = self.otp_periph.as_mut() { + periph.read(size, addr - 0x2000_b000) + } else { + Err(emulator_bus::BusError::LoadAccessFault) + } + } 0x3002_0000..=0x3002_00b4 => { if let Some(periph) = self.mbox_periph.as_mut() { periph.read(size, addr - 0x3002_0000) @@ -115,6 +136,20 @@ impl emulator_bus::Bus for AutoRootBus { Err(emulator_bus::BusError::StoreAccessFault) } } + 0x2000_9000..=0x2000_a9d4 => { + if let Some(periph) = self.entropy_src_periph.as_mut() { + periph.write(size, addr - 0x2000_9000, val) + } else { + Err(emulator_bus::BusError::StoreAccessFault) + } + } + 0x2000_b000..=0x2000_b9dc => { + if let Some(periph) = self.otp_periph.as_mut() { + periph.write(size, addr - 0x2000_b000, val) + } else { + Err(emulator_bus::BusError::StoreAccessFault) + } + } 0x3002_0000..=0x3002_00b4 => { if let Some(periph) = self.mbox_periph.as_mut() { periph.write(size, addr - 0x3002_0000, val) @@ -161,6 +196,12 @@ impl emulator_bus::Bus for AutoRootBus { if let Some(periph) = self.flash_periph.as_mut() { periph.poll(); } + if let Some(periph) = self.entropy_src_periph.as_mut() { + periph.poll(); + } + if let Some(periph) = self.otp_periph.as_mut() { + periph.poll(); + } if let Some(periph) = self.mbox_periph.as_mut() { periph.poll(); } @@ -184,6 +225,12 @@ impl emulator_bus::Bus for AutoRootBus { if let Some(periph) = self.flash_periph.as_mut() { periph.warm_reset(); } + if let Some(periph) = self.entropy_src_periph.as_mut() { + periph.warm_reset(); + } + if let Some(periph) = self.otp_periph.as_mut() { + periph.warm_reset(); + } if let Some(periph) = self.mbox_periph.as_mut() { periph.warm_reset(); } @@ -207,6 +254,12 @@ impl emulator_bus::Bus for AutoRootBus { if let Some(periph) = self.flash_periph.as_mut() { periph.update_reset(); } + if let Some(periph) = self.entropy_src_periph.as_mut() { + periph.update_reset(); + } + if let Some(periph) = self.otp_periph.as_mut() { + periph.update_reset(); + } if let Some(periph) = self.mbox_periph.as_mut() { periph.update_reset(); } diff --git a/registers/generated-emulator/src/sha512_acc.rs b/registers/generated-emulator/src/sha512_acc.rs index d332c41..64e89d5 100644 --- a/registers/generated-emulator/src/sha512_acc.rs +++ b/registers/generated-emulator/src/sha512_acc.rs @@ -78,7 +78,7 @@ pub trait Sha512AccPeripheral { fn read_status( &mut self, _size: emulator_types::RvSize, - ) -> emulator_bus::ReadWriteRegister + ) -> emulator_bus::ReadWriteRegister { emulator_bus::ReadWriteRegister::new(0) } diff --git a/registers/generated-firmware/src/entropy_src.rs b/registers/generated-firmware/src/entropy_src.rs new file mode 100644 index 0000000..c5bd1bf --- /dev/null +++ b/registers/generated-firmware/src/entropy_src.rs @@ -0,0 +1,691 @@ +// Licensed under the Apache-2.0 license. +// +// generated by registers_generator with caliptra-ss repo at a621fff9df7015821eda6f7f73265fef74a01375 +// +pub const ENTROPY_SRC_ADDR: u32 = 0x2000_9000; +pub mod bits { + //! Types that represent individual registers (bitfields). + use tock_registers::register_bitfields; + register_bitfields! { + u32, + pub AdaptpHiThresholds [ + /// This is the threshold size for the adaptive proportion health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the adaptive proportion health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub AdaptpHiWatermarks [ + /// High watermark value of the adaptive proportion test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// High watermark value of the adaptive proportion test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub AdaptpLoThresholds [ + /// This is the threshold size for the adaptive proportion health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is greater than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the adaptive proportion health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is greater than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub AdaptpLoWatermarks [ + /// Low watermark value of the adaptive proportion test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// Low watermark value of the adaptive proportion test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub AlertFailCounts [ + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + RepcntFailCount OFFSET(4) NUMBITS(4) [], + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + AdaptpHiFailCount OFFSET(8) NUMBITS(4) [], + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + AdaptpLoFailCount OFFSET(12) NUMBITS(4) [], + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + BucketFailCount OFFSET(16) NUMBITS(4) [], + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + MarkovHiFailCount OFFSET(20) NUMBITS(4) [], + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + MarkovLoFailCount OFFSET(24) NUMBITS(4) [], + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + RepcntsFailCount OFFSET(28) NUMBITS(4) [], + ], + pub AlertSummaryFailCounts [ + /// This field will hold a running count of + /// the total alert count, which is a sum of all of the other + /// counters in the !!ALERT_FAIL_COUNTS register. + /// It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + AnyFailCount OFFSET(0) NUMBITS(16) [], + ], + pub AlertTest [ + /// Write 1 to trigger one alert event of this kind. + RecovAlert OFFSET(0) NUMBITS(1) [], + /// Write 1 to trigger one alert event of this kind. + FatalAlert OFFSET(1) NUMBITS(1) [], + ], + pub AlertThreshold [ + /// This is the threshold size that will signal an alert when + /// value is reached. A value of zero will disable alerts. + /// The default value is 2. + AlertThreshold OFFSET(0) NUMBITS(16) [], + /// This should be set to the value above, but inverted. + AlertThresholdInv OFFSET(16) NUMBITS(16) [], + ], + pub BucketHiWatermarks [ + /// High watermark value of the bucket test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// High watermark value of the bucket test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub BucketThresholds [ + /// This is the threshold size for the bucket health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the bucket health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub Conf [ + /// Setting this field to kMultiBitBool4True will enable FIPS qualified entropy to be + /// generated. + FipsEnable OFFSET(0) NUMBITS(4) [], + /// Setting this field to kMultiBitBool4True will enable reading entropy values from the + /// ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read + /// input vector is set to the enable encoding. + EntropyDataRegEnable OFFSET(4) NUMBITS(4) [], + /// This field controls the scope (either by-line or by-sum) of the health checks. + /// If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all + /// RNG input lines into a single score, and thresholds will be applied to the sum all + /// the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored + /// individually. A statistical deviation in any one input line, be it due to + /// coincidence or failure, will force rejection of the sample, and count toward the + /// total alert count. + ThresholdScope OFFSET(12) NUMBITS(4) [], + /// Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only + /// one bit is sampled. + RngBitEnable OFFSET(20) NUMBITS(4) [], + /// When the above bit iset, this field selects which bit from the RNG bus will + /// be processed when in single RNG bit mode. + /// This two bit field selects the RNG bit stream: + /// 0b00: RNG bit 0 + /// 0b01: RNG bit 1 + /// 0b10: RNG bit 2 + /// 0b11: RNG bit 3 + RngBitSel OFFSET(24) NUMBITS(2) [], + ], + pub DebugStatus [ + /// This is the depth of the entropy source FIFO. + EntropyFifoDepth OFFSET(0) NUMBITS(3) [], + /// This is the SHA3 finite state machine current state. + Sha3Fsm OFFSET(3) NUMBITS(3) [], + /// This is the SHA3 block processed signal current state. + Sha3BlockPr OFFSET(6) NUMBITS(1) [], + /// This is the SHA3 squeezing signal current state. + Sha3Squeezing OFFSET(7) NUMBITS(1) [], + /// This is the SHA3 absorbed signal current state. + Sha3Absorbed OFFSET(8) NUMBITS(1) [], + /// This is a logic-or of all of the SHA3 error signals. + Sha3Err OFFSET(9) NUMBITS(1) [], + /// The entropy_src main state machine is in the idle state. + MainSmIdle OFFSET(16) NUMBITS(1) [], + /// The entropy_src main state machine is in the boot phase done state. + MainSmBootDone OFFSET(17) NUMBITS(1) [], + ], + pub EntropyControl [ + /// Setting this field to kMultiBitBool4True routes the generated entropy value to the ENTROPY_DATA + /// register to be read by firmware. When this field is kMultiBitBool4False, the generated + /// entropy will be forwarded out of this module to the hardware interface. + EsRoute OFFSET(0) NUMBITS(4) [], + /// Setting this field to kMultiBitBool4True will bypass the conditioning logic and bring raw entropy + /// data to the ENTROPY_DATA register. When kMultiBitBool4False, FIPS compliant entropy + /// will be brought the ENTROPY_DATA register, after being conditioned. + EsType OFFSET(4) NUMBITS(4) [], + ], + pub EntropyInterruptEnable [ + /// Enable interrupt when es_entropy_valid is set. + EsEntropyValid OFFSET(0) NUMBITS(1) [], + /// Enable interrupt when es_health_test_failed is set. + EsHealthTestFailed OFFSET(1) NUMBITS(1) [], + /// Enable interrupt when es_observe_fifo_ready is set. + EsObserveFifoReady OFFSET(2) NUMBITS(1) [], + /// Enable interrupt when es_fatal_err is set. + EsFatalErr OFFSET(3) NUMBITS(1) [], + ], + pub ErrCode [ + /// This bit will be set to one when an error has been detected for the + /// esrng FIFO. The type of error is reflected in the type status + /// bits (bits 28 through 30 of this register). + /// This bit will stay set until the next reset. + SfifoEsrngErr OFFSET(0) NUMBITS(1) [], + /// This bit will be set to one when an error has been detected for the + /// observe FIFO. The type of error is reflected in the type status + /// bits (bits 28 through 30 of this register). + /// This bit will stay set until the next reset. + SfifoObserveErr OFFSET(1) NUMBITS(1) [], + /// This bit will be set to one when an error has been detected for the + /// esfinal FIFO. The type of error is reflected in the type status + /// bits (bits 28 through 30 of this register). + /// This bit will stay set until the next reset. + SfifoEsfinalErr OFFSET(2) NUMBITS(1) [], + /// This bit will be set to one when an illegal state has been detected for the + /// ES ack stage state machine. This error will signal a fatal alert, and also + /// an interrupt if enabled. + /// This bit will stay set until the next reset. + EsAckSmErr OFFSET(20) NUMBITS(1) [], + /// This bit will be set to one when an illegal state has been detected for the + /// ES main stage state machine. This error will signal a fatal alert, and also + /// an interrupt if enabled. + /// This bit will stay set until the next reset. + EsMainSmErr OFFSET(21) NUMBITS(1) [], + /// This bit will be set to one when a hardened counter has detected an error + /// condition. This error will signal a fatal alert, and also + /// an interrupt if enabled. + /// This bit will stay set until the next reset. + EsCntrErr OFFSET(22) NUMBITS(1) [], + /// This bit will be set to one when a SHA3 state error has been detected. + /// This error will signal a fatal alert, and also an interrupt if enabled. + /// This bit will stay set until the next reset. + Sha3StateErr OFFSET(23) NUMBITS(1) [], + /// This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being + /// active has been detected. + /// This error will signal a fatal alert, and also an interrupt if enabled. + /// This bit will stay set until the next reset. + Sha3RstStorageErr OFFSET(24) NUMBITS(1) [], + /// This bit will be set to one when any of the source bits (bits 0 through 1 of this + /// this register) are asserted as a result of an error pulse generated from + /// any full FIFO that has been recieved a write pulse. + /// This bit will stay set until the next reset. + FifoWriteErr OFFSET(28) NUMBITS(1) [], + /// This bit will be set to one when any of the source bits (bits 0 through 1 of this + /// this register) are asserted as a result of an error pulse generated from + /// any empty FIFO that has recieved a read pulse. + /// This bit will stay set until the next reset. + FifoReadErr OFFSET(29) NUMBITS(1) [], + /// This bit will be set to one when any of the source bits (bits 0 through 1 of this + /// this register) are asserted as a result of an error pulse generated from + /// any FIFO where both the empty and full status bits are set. + /// This bit will stay set until the next reset. + FifoStateErr OFFSET(30) NUMBITS(1) [], + ], + pub ErrCodeTest [ + /// Setting this field will set the bit number for which an error + /// will be forced in the hardware. This bit number is that same one + /// found in the !!ERR_CODE register. The action of writing this + /// register will force an error pulse. The sole purpose of this + /// register is to test that any error properly propagates to either + /// an interrupt or an alert. + ErrCodeTest OFFSET(0) NUMBITS(5) [], + ], + pub ExthtFailCounts [ + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + ExthtHiFailCount OFFSET(0) NUMBITS(4) [], + /// This field will hold a running count of test failures that + /// contribute to the total alert count. It will be reset after every + /// passing test sequence. If an alert is signaled, this value + /// will persist until it is cleared. + ExthtLoFailCount OFFSET(4) NUMBITS(4) [], + ], + pub ExthtHiThresholds [ + /// This is the threshold size for the external health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the external health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub ExthtHiWatermarks [ + /// High watermark value of the external health test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// High watermark value of the external health test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub ExthtLoThresholds [ + /// This is the threshold size for the external health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is greater than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the external health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is greater than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub ExthtLoWatermarks [ + /// Low watermark value of the external health test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// Low watermark value of the external health test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub FwOvControl [ + /// Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. + /// In this mode, firmware can monitor the post-health test entropy by reading + /// the observe FIFO. This function also requires that the otp_en_entropy_src_fw_over + /// input vector is set to the enable encoding. + FwOvMode OFFSET(0) NUMBITS(4) [], + /// Setting this field to kMultiBitBool4True will switch the input into the pre-conditioner + /// packer FIFO. Firmware can directly write into the packer FIFO, enabling + /// the ability to insert entropy bits back into the hardware flow. Firmware + /// can read data from the health check packer FIFO, then do optional health + /// checks or optional conditioning, then insert the results back into the flow. + /// Also, the !!FW_OV_CONTROL.FW_OV_MODE bit must be set. + FwOvEntropyInsert OFFSET(4) NUMBITS(4) [], + ], + pub FwOvRdFifoOverflow [ + /// This bit is set by hardware whenever RNG data is lost due to an overflow condition + /// in the Observe FIFO. The RNG data rate is slow enough that firmware should always + /// be able to keep up. This register meanwhile provides an additional check to confirm + /// that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples. + /// If an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied. + FwOvRdFifoOverflow OFFSET(0) NUMBITS(1) [], + ], + pub FwOvSha3Start [ + /// Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine + /// to start the SHA3 process and be ready to accept entropy data. This field should + /// be set prior to writting the FW_OV_WR_DATA register. Once all data has been written, + /// this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish + /// processing and push the result into the ESFINAL FIFO. + /// + /// Note that clearing this bit to kMultiBitBool4False while there is still unprocessed + /// entropy in the !!FW_OV_WR_DATA will start the SHA3 engine before data can be added + /// to the input message, and will also signal a recoverable alert in + /// !!RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that + /// !!FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False. + FwOvInsertStart OFFSET(0) NUMBITS(4) [], + ], + pub FwOvWrFifoFull [ + /// "When this bit is clear, writes to the FW_OV_WR_DATA register are allowed. + /// If this bit is set, it is the equivalent to a FIFO full condition, and writes + /// to the FW_OV_WR_DATA register must be delayed until this bit is reset. + FwOvWrFifoFull OFFSET(0) NUMBITS(1) [], + ], + pub HealthTestWindows [ + /// This is the window size for all health tests. This value is used in normal mode + /// when entropy is being tested in FIPS/CC compliance mode. + /// The default value is (2048 bits * 1 clock/4 bits); + FipsWindow OFFSET(0) NUMBITS(16) [], + /// This is the window size for all health tests when running in bypass mode. This mode + /// is active after reset for the first and only test run, or when this mode is + /// programmed by firmware. + /// The default value is (384 bits * 1 clock/4 bits); + /// + /// Note that currently only a window size of 384 is supported and tested (this + /// corresponds to the register default value 0x60). Do not use any other values, + /// unless you know what you are doing. + BypassWindow OFFSET(16) NUMBITS(16) [], + ], + pub InterruptState [ + /// Asserted when entropy source bits are available. + EsEntropyValid OFFSET(0) NUMBITS(1) [], + /// Asserted when the alert count has been met. + EsHealthTestFailed OFFSET(1) NUMBITS(1) [], + /// Asserted when the observe FIFO has filled to the threshold level. + EsObserveFifoReady OFFSET(2) NUMBITS(1) [], + /// Asserted when a FIFO error occurs, or if an illegal state machine state is reached. + EsFatalErr OFFSET(3) NUMBITS(1) [], + ], + pub InterruptTest [ + /// Write 1 to force es_entropy_valid to 1. + EsEntropyValid OFFSET(0) NUMBITS(1) [], + /// Write 1 to force es_health_test_failed to 1. + EsHealthTestFailed OFFSET(1) NUMBITS(1) [], + /// Write 1 to force es_observe_fifo_ready to 1. + EsObserveFifoReady OFFSET(2) NUMBITS(1) [], + /// Write 1 to force es_fatal_err to 1. + EsFatalErr OFFSET(3) NUMBITS(1) [], + ], + pub MainSmState [ + /// This is the state of the ENTROPY_SRC main state machine. + /// See the RTL file `entropy_src_main_sm` for the meaning of the values. + MainSmState OFFSET(0) NUMBITS(9) [], + ], + pub MarkovHiThresholds [ + /// This is the threshold size for the Markov health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the Markov health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub MarkovHiWatermarks [ + /// High watermark value of the Markov test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// High watermark value of the Markov test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub MarkovLoThresholds [ + /// This is the threshold size for the Markov health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is greater than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the Markov health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is greater than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub MarkovLoWatermarks [ + /// Low watermark value of the Markov test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// Low watermark value of the Markov test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub MeRegwen [ + /// When true, the !!MODULE_ENABLE register can be modified. + /// When false, it becomes read-only. + MeRegwen OFFSET(0) NUMBITS(1) [], + ], + pub ModuleEnable [ + /// Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting + /// this field to kMultiBitBool4False will effectively reset the module. The modules of + /// the entropy complex may only be enabled and disabled in a specific order, see + /// Programmers Guide for details. + ModuleEnable OFFSET(0) NUMBITS(4) [], + ], + pub ObserveFifoDepth [ + /// This field will hold the current depth of the Observe FIFO. + ObserveFifoDepth OFFSET(0) NUMBITS(7) [], + ], + pub ObserveFifoThresh [ + /// This field will set the threshold that the depth of the Observe FIFO + /// will be compared with when setting the interrupt status bit. + /// Note: a value of zero is reserved and not to be used. + ObserveFifoThresh OFFSET(0) NUMBITS(7) [], + ], + pub RecovAlertSts [ + /// This bit is set when the FIPS_ENABLE field in the !!CONF register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + FipsEnableFieldAlert OFFSET(0) NUMBITS(1) [], + /// This bit is set when the ENTROPY_DATA_REG_ENABLE field in the !!CONF register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + EntropyDataRegEnFieldAlert OFFSET(1) NUMBITS(1) [], + /// This bit is set when the MODULE_ENABLE field in the !!MODULE_ENABLE register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + ModuleEnableFieldAlert OFFSET(2) NUMBITS(1) [], + /// This bit is set when the THRESHOLD_SCOPE field in the !!CONF register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + ThresholdScopeFieldAlert OFFSET(3) NUMBITS(1) [], + /// This bit is set when the RNG_BIT_ENABLE field in the !!CONF register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + RngBitEnableFieldAlert OFFSET(5) NUMBITS(1) [], + /// This bit is set when the FW_OV_SHA3_START field in the !!FW_OV_SHA3_START register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + FwOvSha3StartFieldAlert OFFSET(7) NUMBITS(1) [], + /// This bit is set when the FW_OV_MODE field in the !!FW_OV_CONTROL register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + FwOvModeFieldAlert OFFSET(8) NUMBITS(1) [], + /// This bit is set when the FW_OV_ENTROPY_INSERT field in the !!FW_OV_CONTROL register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + FwOvEntropyInsertFieldAlert OFFSET(9) NUMBITS(1) [], + /// This bit is set when the ES_ROUTE field in the !!ENTROPY_CONTROL register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + EsRouteFieldAlert OFFSET(10) NUMBITS(1) [], + /// This bit is set when the ES_TYPE field in the !!ENTROPY_CONTROL register is set to + /// a value other than kMultiBitBool4False or kMultiBitBool4True. + /// Writing a zero resets this status bit. + EsTypeFieldAlert OFFSET(11) NUMBITS(1) [], + /// This bit is set when the main state machine detects a threshhold failure state. + /// Writing a zero resets this status bit. + EsMainSmAlert OFFSET(12) NUMBITS(1) [], + /// This bit is set when the interal entropy bus value is equal to the prior + /// valid value on the bus, indicating a possible attack. + /// Writing a zero resets this status bit. + EsBusCmpAlert OFFSET(13) NUMBITS(1) [], + /// This bit is set when the !!ALERT_THRESHOLD register is not configured properly. + /// The upper field must be the exact inverse of the lower field. + /// Writing a zero resets this status bit. + EsThreshCfgAlert OFFSET(14) NUMBITS(1) [], + /// This bit is set when the packer FIFO has been written but was full at the time, + /// and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes. + /// This alert would normally be the result of not monitoring the !!FW_OV_WR_FIFO_FULL + /// register before each write to the !!FW_OV_WR_DATA register. + /// Writing a zero resets this status bit. + EsFwOvWrAlert OFFSET(15) NUMBITS(1) [], + /// This bit is set when !!FW_OV_SHA3_START has been set to MuBi4 False, without + /// waiting for the FW_OV packer FIFO to clear. The final entropy entry in the FIFO + /// will not be included in the SHA3 digest. (Rather it will be added to the + /// subsequent SHA3 digest.) To avoid this alert, monitor !!FW_OV_WR_FIFO_FULL before + /// clearing !!FW_OV_SHA3_START. This alert only applies when both FW_OV_MODE and + /// FW_OV_ENTROPY_INSERT are set to MuBi4True. + /// Writing a zero resets this status bit. + EsFwOvDisableAlert OFFSET(16) NUMBITS(1) [], + ], + pub Regwen [ + /// This read-only write enable bit will allow write access + /// to control and theshold registers that are associated with this bit, + /// but only when the MODULE_ENABLE field is set to kMultiBitBool4False and the + /// SW_REGUPD write enable bit is set to true. + /// When read as false, these registers become read-only. + Regwen OFFSET(0) NUMBITS(1) [], + ], + pub RepcntsHiWatermarks [ + /// High watermark value of the REPCNTS test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// High watermark value of the REPCNTS test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub RepcntsThresholds [ + /// This is the threshold size for the repetition count symbol health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the repetition count symbol health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub RepcntHiWatermarks [ + /// High watermark value of the REPCNT test in FIPS mode. + FipsWatermark OFFSET(0) NUMBITS(16) [], + /// High watermark value of the REPCNT test in bypass mode. + BypassWatermark OFFSET(16) NUMBITS(16) [], + ], + pub RepcntThresholds [ + /// This is the threshold size for the repetition count health test. + /// This value is used in normal mode when entropy is being tested in + /// FIPS/CC compliance mode. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + FipsThresh OFFSET(0) NUMBITS(16) [], + /// This is the threshold size for the repetition count health test + /// running in bypass mode. This mode is active after reset for the + /// first and only test run, or when this mode is programmed by firmware. + /// This register must be written before the module is enabled. + /// Writing to this register will only update the register if the + /// written value is less than the current value of this register. + /// A read from this register always reflects the current value. + BypassThresh OFFSET(16) NUMBITS(16) [], + ], + pub Rev [ + /// Read of this register shows the ABI of this block. + AbiRevision OFFSET(0) NUMBITS(8) [], + /// Read of this register shows the revision of this block. + HwRevision OFFSET(8) NUMBITS(8) [], + /// Read of this register shows the type of chip using this block. + ChipType OFFSET(16) NUMBITS(8) [], + ], + pub SwRegupd [ + /// When this bit true and the MODULE_ENABLE field is false, + /// the REGWEN write enable bit read as true, and is distributed to + /// all associated control and threshold registers. + /// When false, these registers become read-only. + SwRegupd OFFSET(0) NUMBITS(1) [], + ], + } +} +pub mod regs { + //! Types that represent registers. + use tock_registers::register_structs; + register_structs! { + pub EntropySrc { + (0x0 => pub interrupt_state: tock_registers::registers::ReadWrite), + (0x4 => pub entropy_interrupt_enable: tock_registers::registers::ReadWrite), + (0x8 => pub interrupt_test: tock_registers::registers::WriteOnly), + (0xc => pub alert_test: tock_registers::registers::WriteOnly), + (0x10 => pub me_regwen: tock_registers::registers::ReadWrite), + (0x14 => pub sw_regupd: tock_registers::registers::ReadWrite), + (0x18 => pub regwen: tock_registers::registers::ReadOnly), + (0x1c => pub rev: tock_registers::registers::ReadOnly), + (0x20 => pub module_enable: tock_registers::registers::ReadWrite), + (0x24 => pub conf: tock_registers::registers::ReadWrite), + (0x28 => pub entropy_control: tock_registers::registers::ReadWrite), + (0x2c => pub entropy_data: tock_registers::registers::ReadOnly), + (0x30 => pub health_test_windows: tock_registers::registers::ReadWrite), + (0x34 => pub repcnt_thresholds: tock_registers::registers::ReadWrite), + (0x38 => pub repcnts_thresholds: tock_registers::registers::ReadWrite), + (0x3c => pub adaptp_hi_thresholds: tock_registers::registers::ReadWrite), + (0x40 => pub adaptp_lo_thresholds: tock_registers::registers::ReadWrite), + (0x44 => pub bucket_thresholds: tock_registers::registers::ReadWrite), + (0x48 => pub markov_hi_thresholds: tock_registers::registers::ReadWrite), + (0x4c => pub markov_lo_thresholds: tock_registers::registers::ReadWrite), + (0x50 => pub extht_hi_thresholds: tock_registers::registers::ReadWrite), + (0x54 => pub extht_lo_thresholds: tock_registers::registers::ReadWrite), + (0x58 => pub repcnt_hi_watermarks: tock_registers::registers::ReadOnly), + (0x5c => pub repcnts_hi_watermarks: tock_registers::registers::ReadOnly), + (0x60 => pub adaptp_hi_watermarks: tock_registers::registers::ReadOnly), + (0x64 => pub adaptp_lo_watermarks: tock_registers::registers::ReadOnly), + (0x68 => pub extht_hi_watermarks: tock_registers::registers::ReadOnly), + (0x6c => pub extht_lo_watermarks: tock_registers::registers::ReadOnly), + (0x70 => pub bucket_hi_watermarks: tock_registers::registers::ReadOnly), + (0x74 => pub markov_hi_watermarks: tock_registers::registers::ReadOnly), + (0x78 => pub markov_lo_watermarks: tock_registers::registers::ReadOnly), + (0x7c => pub repcnt_total_fails: tock_registers::registers::ReadOnly), + (0x80 => pub repcnts_total_fails: tock_registers::registers::ReadOnly), + (0x84 => pub adaptp_hi_total_fails: tock_registers::registers::ReadOnly), + (0x88 => pub adaptp_lo_total_fails: tock_registers::registers::ReadOnly), + (0x8c => pub bucket_total_fails: tock_registers::registers::ReadOnly), + (0x90 => pub markov_hi_total_fails: tock_registers::registers::ReadOnly), + (0x94 => pub markov_lo_total_fails: tock_registers::registers::ReadOnly), + (0x98 => pub extht_hi_total_fails: tock_registers::registers::ReadOnly), + (0x9c => pub extht_lo_total_fails: tock_registers::registers::ReadOnly), + (0xa0 => pub alert_threshold: tock_registers::registers::ReadWrite), + (0xa4 => pub alert_summary_fail_counts: tock_registers::registers::ReadOnly), + (0xa8 => pub alert_fail_counts: tock_registers::registers::ReadOnly), + (0xac => pub extht_fail_counts: tock_registers::registers::ReadOnly), + (0xb0 => pub fw_ov_control: tock_registers::registers::ReadWrite), + (0xb4 => pub fw_ov_sha3_start: tock_registers::registers::ReadWrite), + (0xb8 => pub fw_ov_wr_fifo_full: tock_registers::registers::ReadOnly), + (0xbc => pub fw_ov_rd_fifo_overflow: tock_registers::registers::ReadOnly), + (0xc0 => pub fw_ov_rd_data: tock_registers::registers::ReadOnly), + (0xc4 => pub fw_ov_wr_data: tock_registers::registers::WriteOnly), + (0xc8 => pub observe_fifo_thresh: tock_registers::registers::ReadWrite), + (0xcc => pub observe_fifo_depth: tock_registers::registers::ReadOnly), + (0xd0 => pub debug_status: tock_registers::registers::ReadOnly), + (0xd4 => pub recov_alert_sts: tock_registers::registers::ReadWrite), + (0xd8 => pub err_code: tock_registers::registers::ReadOnly), + (0xdc => pub err_code_test: tock_registers::registers::ReadWrite), + (0xe0 => pub main_sm_state: tock_registers::registers::ReadOnly), + (0xe4 => @END), + } + } +} diff --git a/registers/generated-firmware/src/i3c.rs b/registers/generated-firmware/src/i3c.rs index 9cd30e2..ba8c2b0 100644 --- a/registers/generated-firmware/src/i3c.rs +++ b/registers/generated-firmware/src/i3c.rs @@ -837,131 +837,131 @@ pub mod regs { use tock_registers::register_structs; register_structs! { pub I3c { - (0x0 => pub hci_version: tock_registers::registers::ReadOnly), - (0x4 => pub hc_control: tock_registers::registers::ReadWrite), - (0x8 => pub controller_device_addr: tock_registers::registers::ReadWrite), - (0xc => pub hc_capabilities: tock_registers::registers::ReadOnly), - (0x10 => pub reset_control: tock_registers::registers::ReadWrite), - (0x14 => pub present_state: tock_registers::registers::ReadOnly), + (0x0 => pub i3c_base_hci_version: tock_registers::registers::ReadOnly), + (0x4 => pub i3c_base_hc_control: tock_registers::registers::ReadWrite), + (0x8 => pub i3c_base_controller_device_addr: tock_registers::registers::ReadWrite), + (0xc => pub i3c_base_hc_capabilities: tock_registers::registers::ReadOnly), + (0x10 => pub i3c_base_reset_control: tock_registers::registers::ReadWrite), + (0x14 => pub i3c_base_present_state: tock_registers::registers::ReadOnly), (0x18 => _reserved0), - (0x20 => pub intr_status: tock_registers::registers::ReadWrite), - (0x24 => pub intr_status_enable: tock_registers::registers::ReadWrite), - (0x28 => pub intr_signal_enable: tock_registers::registers::ReadWrite), - (0x2c => pub intr_force: tock_registers::registers::WriteOnly), - (0x30 => pub dat_section_offset: tock_registers::registers::ReadOnly), - (0x34 => pub dct_section_offset: tock_registers::registers::ReadWrite), - (0x38 => pub ring_headers_section_offset: tock_registers::registers::ReadOnly), - (0x3c => pub pio_section_offset: tock_registers::registers::ReadOnly), - (0x40 => pub ext_caps_section_offset: tock_registers::registers::ReadOnly), + (0x20 => pub i3c_base_intr_status: tock_registers::registers::ReadWrite), + (0x24 => pub i3c_base_intr_status_enable: tock_registers::registers::ReadWrite), + (0x28 => pub i3c_base_intr_signal_enable: tock_registers::registers::ReadWrite), + (0x2c => pub i3c_base_intr_force: tock_registers::registers::WriteOnly), + (0x30 => pub i3c_base_dat_section_offset: tock_registers::registers::ReadOnly), + (0x34 => pub i3c_base_dct_section_offset: tock_registers::registers::ReadWrite), + (0x38 => pub i3c_base_ring_headers_section_offset: tock_registers::registers::ReadOnly), + (0x3c => pub i3c_base_pio_section_offset: tock_registers::registers::ReadOnly), + (0x40 => pub i3c_base_ext_caps_section_offset: tock_registers::registers::ReadOnly), (0x44 => _reserved1), - (0x4c => pub int_ctrl_cmds_en: tock_registers::registers::ReadOnly), + (0x4c => pub i3c_base_int_ctrl_cmds_en: tock_registers::registers::ReadOnly), (0x50 => _reserved2), - (0x58 => pub ibi_notify_ctrl: tock_registers::registers::ReadWrite), - (0x5c => pub ibi_data_abort_ctrl: tock_registers::registers::ReadWrite), - (0x60 => pub dev_ctx_base_lo: tock_registers::registers::ReadWrite), - (0x64 => pub dev_ctx_base_hi: tock_registers::registers::ReadWrite), - (0x68 => pub dev_ctx_sg: tock_registers::registers::ReadOnly), + (0x58 => pub i3c_base_ibi_notify_ctrl: tock_registers::registers::ReadWrite), + (0x5c => pub i3c_base_ibi_data_abort_ctrl: tock_registers::registers::ReadWrite), + (0x60 => pub i3c_base_dev_ctx_base_lo: tock_registers::registers::ReadWrite), + (0x64 => pub i3c_base_dev_ctx_base_hi: tock_registers::registers::ReadWrite), + (0x68 => pub i3c_base_dev_ctx_sg: tock_registers::registers::ReadOnly), (0x6c => _reserved3), - (0x80 => pub command_port: tock_registers::registers::WriteOnly), - (0x84 => pub response_port: tock_registers::registers::ReadOnly), - (0x88 => pub tx_data_port: tock_registers::registers::WriteOnly), - (0x8c => pub ibi_port: tock_registers::registers::ReadOnly), - (0x90 => pub queue_thld_ctrl: tock_registers::registers::ReadWrite), - (0x94 => pub data_buffer_thld_ctrl: tock_registers::registers::ReadWrite), - (0x98 => pub queue_size: tock_registers::registers::ReadOnly), - (0x9c => pub alt_queue_size: tock_registers::registers::ReadOnly), - (0xa0 => pub pio_intr_status: tock_registers::registers::ReadWrite), - (0xa4 => pub pio_intr_status_enable: tock_registers::registers::ReadWrite), - (0xa8 => pub pio_intr_signal_enable: tock_registers::registers::ReadWrite), - (0xac => pub pio_intr_force: tock_registers::registers::WriteOnly), - (0xb0 => pub pio_control: tock_registers::registers::ReadWrite), + (0x80 => pub piocontrol_command_port: tock_registers::registers::WriteOnly), + (0x84 => pub piocontrol_response_port: tock_registers::registers::ReadOnly), + (0x88 => pub piocontrol_tx_data_port: tock_registers::registers::WriteOnly), + (0x8c => pub piocontrol_ibi_port: tock_registers::registers::ReadOnly), + (0x90 => pub piocontrol_queue_thld_ctrl: tock_registers::registers::ReadWrite), + (0x94 => pub piocontrol_data_buffer_thld_ctrl: tock_registers::registers::ReadWrite), + (0x98 => pub piocontrol_queue_size: tock_registers::registers::ReadOnly), + (0x9c => pub piocontrol_alt_queue_size: tock_registers::registers::ReadOnly), + (0xa0 => pub piocontrol_pio_intr_status: tock_registers::registers::ReadWrite), + (0xa4 => pub piocontrol_pio_intr_status_enable: tock_registers::registers::ReadWrite), + (0xa8 => pub piocontrol_pio_intr_signal_enable: tock_registers::registers::ReadWrite), + (0xac => pub piocontrol_pio_intr_force: tock_registers::registers::WriteOnly), + (0xb0 => pub piocontrol_pio_control: tock_registers::registers::ReadWrite), (0xb4 => _reserved4), - (0x100 => pub termination_extcap_header: tock_registers::registers::ReadOnly), - (0x104 => pub prot_cap_0: tock_registers::registers::ReadWrite), - (0x108 => pub prot_cap_1: tock_registers::registers::ReadWrite), - (0x10c => pub prot_cap_2: tock_registers::registers::ReadWrite), - (0x110 => pub prot_cap_3: tock_registers::registers::ReadWrite), - (0x114 => pub device_id_0: tock_registers::registers::ReadWrite), - (0x118 => pub device_id_1: tock_registers::registers::ReadWrite), - (0x11c => pub device_id_2: tock_registers::registers::ReadWrite), - (0x120 => pub device_id_3: tock_registers::registers::ReadWrite), - (0x124 => pub device_id_4: tock_registers::registers::ReadWrite), - (0x128 => pub device_id_5: tock_registers::registers::ReadWrite), - (0x12c => pub device_id_6: tock_registers::registers::ReadWrite), - (0x130 => pub device_status_0: tock_registers::registers::ReadWrite), - (0x134 => pub device_status_1: tock_registers::registers::ReadWrite), - (0x138 => pub device_reset: tock_registers::registers::ReadWrite), - (0x13c => pub recovery_ctrl: tock_registers::registers::ReadWrite), - (0x140 => pub recovery_status: tock_registers::registers::ReadWrite), - (0x144 => pub hw_status: tock_registers::registers::ReadWrite), - (0x148 => pub indirect_fifo_ctrl_0: tock_registers::registers::ReadWrite), - (0x14c => pub indirect_fifo_ctrl_1: tock_registers::registers::ReadWrite), - (0x150 => pub indirect_fifo_status_0: tock_registers::registers::ReadWrite), - (0x154 => pub indirect_fifo_status_1: tock_registers::registers::ReadWrite), - (0x158 => pub indirect_fifo_status_2: tock_registers::registers::ReadWrite), - (0x15c => pub indirect_fifo_status_3: tock_registers::registers::ReadWrite), - (0x160 => pub indirect_fifo_status_4: tock_registers::registers::ReadWrite), - (0x164 => pub indirect_fifo_status_5: tock_registers::registers::ReadWrite), - (0x168 => pub indirect_fifo_data: tock_registers::registers::ReadWrite), + (0x100 => pub i3c_ec_termination_extcap_header: tock_registers::registers::ReadOnly), + (0x104 => pub sec_fw_recovery_if_prot_cap_0: tock_registers::registers::ReadWrite), + (0x108 => pub sec_fw_recovery_if_prot_cap_1: tock_registers::registers::ReadWrite), + (0x10c => pub sec_fw_recovery_if_prot_cap_2: tock_registers::registers::ReadWrite), + (0x110 => pub sec_fw_recovery_if_prot_cap_3: tock_registers::registers::ReadWrite), + (0x114 => pub sec_fw_recovery_if_device_id_0: tock_registers::registers::ReadWrite), + (0x118 => pub sec_fw_recovery_if_device_id_1: tock_registers::registers::ReadWrite), + (0x11c => pub sec_fw_recovery_if_device_id_2: tock_registers::registers::ReadWrite), + (0x120 => pub sec_fw_recovery_if_device_id_3: tock_registers::registers::ReadWrite), + (0x124 => pub sec_fw_recovery_if_device_id_4: tock_registers::registers::ReadWrite), + (0x128 => pub sec_fw_recovery_if_device_id_5: tock_registers::registers::ReadWrite), + (0x12c => pub sec_fw_recovery_if_device_id_6: tock_registers::registers::ReadWrite), + (0x130 => pub sec_fw_recovery_if_device_status_0: tock_registers::registers::ReadWrite), + (0x134 => pub sec_fw_recovery_if_device_status_1: tock_registers::registers::ReadWrite), + (0x138 => pub sec_fw_recovery_if_device_reset: tock_registers::registers::ReadWrite), + (0x13c => pub sec_fw_recovery_if_recovery_ctrl: tock_registers::registers::ReadWrite), + (0x140 => pub sec_fw_recovery_if_recovery_status: tock_registers::registers::ReadWrite), + (0x144 => pub sec_fw_recovery_if_hw_status: tock_registers::registers::ReadWrite), + (0x148 => pub sec_fw_recovery_if_indirect_fifo_ctrl_0: tock_registers::registers::ReadWrite), + (0x14c => pub sec_fw_recovery_if_indirect_fifo_ctrl_1: tock_registers::registers::ReadWrite), + (0x150 => pub sec_fw_recovery_if_indirect_fifo_status_0: tock_registers::registers::ReadWrite), + (0x154 => pub sec_fw_recovery_if_indirect_fifo_status_1: tock_registers::registers::ReadWrite), + (0x158 => pub sec_fw_recovery_if_indirect_fifo_status_2: tock_registers::registers::ReadWrite), + (0x15c => pub sec_fw_recovery_if_indirect_fifo_status_3: tock_registers::registers::ReadWrite), + (0x160 => pub sec_fw_recovery_if_indirect_fifo_status_4: tock_registers::registers::ReadWrite), + (0x164 => pub sec_fw_recovery_if_indirect_fifo_status_5: tock_registers::registers::ReadWrite), + (0x168 => pub sec_fw_recovery_if_indirect_fifo_data: tock_registers::registers::ReadWrite), (0x16c => _reserved5), - (0x180 => pub extcap_header0: tock_registers::registers::ReadOnly), - (0x184 => pub stby_cr_control: tock_registers::registers::ReadWrite), - (0x188 => pub stby_cr_device_addr: tock_registers::registers::ReadWrite), - (0x18c => pub stby_cr_capabilities: tock_registers::registers::ReadWrite), - (0x190 => pub _rsvd_0: tock_registers::registers::ReadWrite), - (0x194 => pub stby_cr_status: tock_registers::registers::ReadWrite), - (0x198 => pub stby_cr_device_char: tock_registers::registers::ReadWrite), - (0x19c => pub stby_cr_device_pid_lo: tock_registers::registers::ReadWrite), - (0x1a0 => pub stby_cr_intr_status: tock_registers::registers::ReadWrite), - (0x1a4 => pub _rsvd_1: tock_registers::registers::ReadWrite), - (0x1a8 => pub stby_cr_intr_signal_enable: tock_registers::registers::ReadWrite), - (0x1ac => pub stby_cr_intr_force: tock_registers::registers::ReadWrite), - (0x1b0 => pub stby_cr_ccc_config_getcaps: tock_registers::registers::ReadWrite), - (0x1b4 => pub stby_cr_ccc_config_rstact_params: tock_registers::registers::ReadWrite), - (0x1b8 => pub _rsvd_2: tock_registers::registers::ReadWrite), - (0x1bc => pub _rsvd_3: tock_registers::registers::ReadWrite), - (0x1c0 => pub extcap_header1: tock_registers::registers::ReadOnly), - (0x1c4 => pub control: tock_registers::registers::ReadWrite), - (0x1c8 => pub status: tock_registers::registers::ReadWrite), - (0x1cc => pub tti_reset_control: tock_registers::registers::ReadWrite), - (0x1d0 => pub interrupt_status: tock_registers::registers::ReadWrite), - (0x1d4 => pub interrupt_enable: tock_registers::registers::ReadWrite), - (0x1d8 => pub interrupt_force: tock_registers::registers::ReadWrite), - (0x1dc => pub rx_desc_queue_port: tock_registers::registers::ReadOnly), - (0x1e0 => pub rx_data_port0: tock_registers::registers::ReadOnly), - (0x1e4 => pub tx_desc_queue_port: tock_registers::registers::WriteOnly), - (0x1e8 => pub tx_data_port0: tock_registers::registers::WriteOnly), - (0x1ec => pub tti_ibi_port: tock_registers::registers::WriteOnly), - (0x1f0 => pub tti_queue_size: tock_registers::registers::ReadOnly), - (0x1f4 => pub ibi_tti_queue_size: tock_registers::registers::ReadOnly), - (0x1f8 => pub tti_queue_thld_ctrl: tock_registers::registers::ReadWrite), - (0x1fc => pub tti_data_buffer_thld_ctrl: tock_registers::registers::ReadWrite), - (0x200 => pub extcap_header2: tock_registers::registers::ReadOnly), - (0x204 => pub soc_mgmt_control: tock_registers::registers::ReadWrite), - (0x208 => pub soc_mgmt_status: tock_registers::registers::ReadWrite), - (0x20c => pub soc_mgmt_rsvd_0: tock_registers::registers::ReadWrite), - (0x210 => pub soc_mgmt_rsvd_1: tock_registers::registers::ReadWrite), - (0x214 => pub soc_mgmt_rsvd_2: tock_registers::registers::ReadWrite), - (0x218 => pub soc_mgmt_rsvd_3: tock_registers::registers::ReadWrite), - (0x21c => pub soc_pad_conf: tock_registers::registers::ReadWrite), - (0x220 => pub soc_pad_attr: tock_registers::registers::ReadWrite), - (0x224 => pub soc_mgmt_feature_2: tock_registers::registers::ReadWrite), - (0x228 => pub soc_mgmt_feature_3: tock_registers::registers::ReadWrite), - (0x22c => pub t_r_reg: tock_registers::registers::ReadWrite), - (0x230 => pub t_f_reg: tock_registers::registers::ReadWrite), - (0x234 => pub t_su_dat_reg: tock_registers::registers::ReadWrite), - (0x238 => pub t_hd_dat_reg: tock_registers::registers::ReadWrite), - (0x23c => pub t_high_reg: tock_registers::registers::ReadWrite), - (0x240 => pub t_low_reg: tock_registers::registers::ReadWrite), - (0x244 => pub t_hd_sta_reg: tock_registers::registers::ReadWrite), - (0x248 => pub t_su_sta_reg: tock_registers::registers::ReadWrite), - (0x24c => pub t_su_sto_reg: tock_registers::registers::ReadWrite), - (0x250 => pub t_free_reg: tock_registers::registers::ReadWrite), - (0x254 => pub t_aval_reg: tock_registers::registers::ReadWrite), - (0x258 => pub t_idle_reg: tock_registers::registers::ReadWrite), + (0x180 => pub stdby_ctrl_mode_extcap_header: tock_registers::registers::ReadOnly), + (0x184 => pub stdby_ctrl_mode_stby_cr_control: tock_registers::registers::ReadWrite), + (0x188 => pub stdby_ctrl_mode_stby_cr_device_addr: tock_registers::registers::ReadWrite), + (0x18c => pub stdby_ctrl_mode_stby_cr_capabilities: tock_registers::registers::ReadWrite), + (0x190 => pub stdby_ctrl_mode_rsvd_0: tock_registers::registers::ReadWrite), + (0x194 => pub stdby_ctrl_mode_stby_cr_status: tock_registers::registers::ReadWrite), + (0x198 => pub stdby_ctrl_mode_stby_cr_device_char: tock_registers::registers::ReadWrite), + (0x19c => pub stdby_ctrl_mode_stby_cr_device_pid_lo: tock_registers::registers::ReadWrite), + (0x1a0 => pub stdby_ctrl_mode_stby_cr_intr_status: tock_registers::registers::ReadWrite), + (0x1a4 => pub stdby_ctrl_mode_rsvd_1: tock_registers::registers::ReadWrite), + (0x1a8 => pub stdby_ctrl_mode_stby_cr_intr_signal_enable: tock_registers::registers::ReadWrite), + (0x1ac => pub stdby_ctrl_mode_stby_cr_intr_force: tock_registers::registers::ReadWrite), + (0x1b0 => pub stdby_ctrl_mode_stby_cr_ccc_config_getcaps: tock_registers::registers::ReadWrite), + (0x1b4 => pub stdby_ctrl_mode_stby_cr_ccc_config_rstact_params: tock_registers::registers::ReadWrite), + (0x1b8 => pub stdby_ctrl_mode_rsvd_2: tock_registers::registers::ReadWrite), + (0x1bc => pub stdby_ctrl_mode_rsvd_3: tock_registers::registers::ReadWrite), + (0x1c0 => pub tti_extcap_header: tock_registers::registers::ReadOnly), + (0x1c4 => pub tti_control: tock_registers::registers::ReadWrite), + (0x1c8 => pub tti_status: tock_registers::registers::ReadWrite), + (0x1cc => pub tti_tti_reset_control: tock_registers::registers::ReadWrite), + (0x1d0 => pub tti_interrupt_status: tock_registers::registers::ReadWrite), + (0x1d4 => pub tti_interrupt_enable: tock_registers::registers::ReadWrite), + (0x1d8 => pub tti_interrupt_force: tock_registers::registers::ReadWrite), + (0x1dc => pub tti_rx_desc_queue_port: tock_registers::registers::ReadOnly), + (0x1e0 => pub tti_rx_data_port: tock_registers::registers::ReadOnly), + (0x1e4 => pub tti_tx_desc_queue_port: tock_registers::registers::WriteOnly), + (0x1e8 => pub tti_tx_data_port: tock_registers::registers::WriteOnly), + (0x1ec => pub tti_tti_ibi_port: tock_registers::registers::WriteOnly), + (0x1f0 => pub tti_tti_queue_size: tock_registers::registers::ReadOnly), + (0x1f4 => pub tti_ibi_tti_queue_size: tock_registers::registers::ReadOnly), + (0x1f8 => pub tti_tti_queue_thld_ctrl: tock_registers::registers::ReadWrite), + (0x1fc => pub tti_tti_data_buffer_thld_ctrl: tock_registers::registers::ReadWrite), + (0x200 => pub soc_mgmt_if_extcap_header: tock_registers::registers::ReadOnly), + (0x204 => pub soc_mgmt_if_soc_mgmt_control: tock_registers::registers::ReadWrite), + (0x208 => pub soc_mgmt_if_soc_mgmt_status: tock_registers::registers::ReadWrite), + (0x20c => pub soc_mgmt_if_soc_mgmt_rsvd_0: tock_registers::registers::ReadWrite), + (0x210 => pub soc_mgmt_if_soc_mgmt_rsvd_1: tock_registers::registers::ReadWrite), + (0x214 => pub soc_mgmt_if_soc_mgmt_rsvd_2: tock_registers::registers::ReadWrite), + (0x218 => pub soc_mgmt_if_soc_mgmt_rsvd_3: tock_registers::registers::ReadWrite), + (0x21c => pub soc_mgmt_if_soc_pad_conf: tock_registers::registers::ReadWrite), + (0x220 => pub soc_mgmt_if_soc_pad_attr: tock_registers::registers::ReadWrite), + (0x224 => pub soc_mgmt_if_soc_mgmt_feature_2: tock_registers::registers::ReadWrite), + (0x228 => pub soc_mgmt_if_soc_mgmt_feature_3: tock_registers::registers::ReadWrite), + (0x22c => pub soc_mgmt_if_t_r_reg: tock_registers::registers::ReadWrite), + (0x230 => pub soc_mgmt_if_t_f_reg: tock_registers::registers::ReadWrite), + (0x234 => pub soc_mgmt_if_t_su_dat_reg: tock_registers::registers::ReadWrite), + (0x238 => pub soc_mgmt_if_t_hd_dat_reg: tock_registers::registers::ReadWrite), + (0x23c => pub soc_mgmt_if_t_high_reg: tock_registers::registers::ReadWrite), + (0x240 => pub soc_mgmt_if_t_low_reg: tock_registers::registers::ReadWrite), + (0x244 => pub soc_mgmt_if_t_hd_sta_reg: tock_registers::registers::ReadWrite), + (0x248 => pub soc_mgmt_if_t_su_sta_reg: tock_registers::registers::ReadWrite), + (0x24c => pub soc_mgmt_if_t_su_sto_reg: tock_registers::registers::ReadWrite), + (0x250 => pub soc_mgmt_if_t_free_reg: tock_registers::registers::ReadWrite), + (0x254 => pub soc_mgmt_if_t_aval_reg: tock_registers::registers::ReadWrite), + (0x258 => pub soc_mgmt_if_t_idle_reg: tock_registers::registers::ReadWrite), (0x25c => _reserved6), - (0x260 => pub extcap_header3: tock_registers::registers::ReadOnly), - (0x264 => pub controller_config: tock_registers::registers::ReadOnly), + (0x260 => pub ctrl_cfg_extcap_header: tock_registers::registers::ReadOnly), + (0x264 => pub ctrl_cfg_controller_config: tock_registers::registers::ReadOnly), (0x268 => _reserved7), (0x400 => pub dat: [tock_registers::registers::ReadWrite; 256]), (0x800 => pub dct: [tock_registers::registers::ReadWrite; 512]), diff --git a/registers/generated-firmware/src/lib.rs b/registers/generated-firmware/src/lib.rs index 583380a..d570fb8 100644 --- a/registers/generated-firmware/src/lib.rs +++ b/registers/generated-firmware/src/lib.rs @@ -5,9 +5,11 @@ #![recursion_limit = "256"] #![no_std] pub mod el2_pic_ctrl; +pub mod entropy_src; pub mod flash_ctrl; pub mod i3c; pub mod mbox; +pub mod otp_ctrl; pub mod sha512_acc; pub mod soc_ifc; pub mod soc_ifc_trng; diff --git a/registers/generated-firmware/src/otp_ctrl.rs b/registers/generated-firmware/src/otp_ctrl.rs new file mode 100644 index 0000000..0157931 --- /dev/null +++ b/registers/generated-firmware/src/otp_ctrl.rs @@ -0,0 +1,250 @@ +// Licensed under the Apache-2.0 license. +// +// generated by registers_generator with caliptra-ss repo at a621fff9df7015821eda6f7f73265fef74a01375 +// +pub const CALIPTRA_OTP_CTRL_ADDR: u32 = 0x2000_b000; +pub mod bits { + //! Types that represent individual registers (bitfields). + use tock_registers::register_bitfields; + register_bitfields! { + u32, + pub AlertTest [ + /// Write 1 to trigger one alert event of this kind. + FatalMacrError OFFSET(0) NUMBITS(1) [], + /// Write 1 to trigger one alert event of this kind. + FatalCheckError OFFSET(1) NUMBITS(1) [], + /// Write 1 to trigger one alert event of this kind. + FatalBusIntegError OFFSET(2) NUMBITS(1) [], + /// Write 1 to trigger one alert event of this kind. + FatalPrimOtpAlert OFFSET(3) NUMBITS(1) [], + /// Write 1 to trigger one alert event of this kind. + RecovPrimOtpAlert OFFSET(4) NUMBITS(1) [], + ], + pub CheckRegwen [ + /// When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore.\nWrite 0 to clear this bit. + Regwen OFFSET(0) NUMBITS(1) [], + ], + pub CheckTrigger [ + /// Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING + /// and wait until the check has been completed. If there are any errors, those will be flagged + /// in the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts. + Integrity OFFSET(0) NUMBITS(1) [], + /// Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts. + Consistency OFFSET(1) NUMBITS(1) [], + ], + pub CheckTriggerRegwen [ + /// When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore. + /// Write 0 to clear this bit. + Regwen OFFSET(0) NUMBITS(1) [], + ], + pub Csr0 [ + Field0 OFFSET(0) NUMBITS(1) [], + Field1 OFFSET(1) NUMBITS(1) [], + Field2 OFFSET(2) NUMBITS(1) [], + Field3 OFFSET(4) NUMBITS(10) [], + Field4 OFFSET(16) NUMBITS(11) [], + ], + pub Csr1 [ + Field0 OFFSET(0) NUMBITS(7) [], + Field1 OFFSET(7) NUMBITS(1) [], + Field2 OFFSET(8) NUMBITS(7) [], + Field3 OFFSET(15) NUMBITS(1) [], + Field4 OFFSET(16) NUMBITS(16) [], + ], + pub Csr2 [ + Field0 OFFSET(0) NUMBITS(1) [], + ], + pub Csr3 [ + Field0 OFFSET(0) NUMBITS(3) [], + Field1 OFFSET(4) NUMBITS(10) [], + Field2 OFFSET(16) NUMBITS(1) [], + Field3 OFFSET(17) NUMBITS(1) [], + Field4 OFFSET(18) NUMBITS(1) [], + Field5 OFFSET(19) NUMBITS(1) [], + Field6 OFFSET(20) NUMBITS(1) [], + Field7 OFFSET(21) NUMBITS(1) [], + Field8 OFFSET(22) NUMBITS(1) [], + ], + pub Csr4 [ + Field0 OFFSET(0) NUMBITS(10) [], + Field1 OFFSET(12) NUMBITS(1) [], + Field2 OFFSET(13) NUMBITS(1) [], + Field3 OFFSET(14) NUMBITS(1) [], + ], + pub Csr5 [ + Field0 OFFSET(0) NUMBITS(6) [], + Field1 OFFSET(6) NUMBITS(2) [], + Field2 OFFSET(8) NUMBITS(8) [], + Field3 OFFSET(9) NUMBITS(3) [], + Field4 OFFSET(12) NUMBITS(12) [], + Field5 OFFSET(24) NUMBITS(13) [], + Field6 OFFSET(16) NUMBITS(16) [], + ], + pub Csr6 [ + Field0 OFFSET(0) NUMBITS(10) [], + Field1 OFFSET(11) NUMBITS(1) [], + Field2 OFFSET(12) NUMBITS(1) [], + Field3 OFFSET(16) NUMBITS(16) [], + ], + pub Csr7 [ + Field0 OFFSET(0) NUMBITS(6) [], + Field1 OFFSET(8) NUMBITS(3) [], + Field2 OFFSET(14) NUMBITS(1) [], + Field3 OFFSET(15) NUMBITS(1) [], + ], + pub DirectAccessAddress [ + /// This is the address for the OTP word to be read or written thrugh\nthe direct access interface. Note that the address is aligned to the access size\ninternally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored\nfor 64bit accesses.\n\nFor the digest calculation command, set this register to the partition base offset. + Address OFFSET(0) NUMBITS(12) [], + ], + pub DirectAccessCmd [ + /// Initiates a readout sequence that reads the location specified\nby !!DIRECT_ACCESS_ADDRESS. The command places the data read into\n!!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions). + Rd OFFSET(0) NUMBITS(1) [], + /// Initiates a prgramming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0\nand !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by\n!!DIRECT_ACCESS_ADDRESS. + Wr OFFSET(1) NUMBITS(1) [], + /// Initiates the digest calculation and locking sequence for the partition specified by\n!!DIRECT_ACCESS_ADDRESS. + Digest OFFSET(2) NUMBITS(1) [], + ], + pub DirectAccessRegwen [ + /// This bit contrls whether the DAI registers can be written.\nWrite 0 to it in order to clear the bit.\n\nNote that the hardware also modulates this bit and sets it to 0 temporarily\nduring an OTP operation such that the corresponding address and data registers\ncannot be modified while an operation is pending. The !!DAI_IDLE status bit\nwill also be set to 0 in such a case. + Regwen OFFSET(0) NUMBITS(1) [], + ], + pub InterruptState [ + /// A direct access command or digest calculation operation has completed. + OtpOperationDone OFFSET(0) NUMBITS(1) [], + /// An error has occurred in the OTP contrller. Check the !!ERR_CODE register to get more information. + OtpError OFFSET(1) NUMBITS(1) [], + ], + pub InterruptTest [ + /// Write 1 to force otp_operation_done to 1. + OtpOperationDone OFFSET(0) NUMBITS(1) [], + /// Write 1 to force otp_error to 1. + OtpError OFFSET(1) NUMBITS(1) [], + ], + pub NonSecretFusesReadLock [ + /// When cleared to 0, read access to the NON_SECRET_FUSES_READ_LOCK partition is locked.\nWrite 0 to clear this bit. + ReadLock OFFSET(0) NUMBITS(1) [], + ], + pub OtpInterruptEnable [ + /// Enable interrupt when otp_operation_done is set. + OtpOperationDone OFFSET(0) NUMBITS(1) [], + /// Enable interrupt when otp_error is set. + OtpError OFFSET(1) NUMBITS(1) [], + ], + pub Status [ + /// Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + VendorTestError OFFSET(0) NUMBITS(1) [], + /// Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + NonSecretFusesError OFFSET(1) NUMBITS(1) [], + /// Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + Secret0Error OFFSET(2) NUMBITS(1) [], + /// Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + Secret1Error OFFSET(3) NUMBITS(1) [], + /// Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + Secret2Error OFFSET(4) NUMBITS(1) [], + /// Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + Secret3Error OFFSET(5) NUMBITS(1) [], + /// Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + LifeCycleError OFFSET(6) NUMBITS(1) [], + /// Set to 1 if an error occurred in the DAI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + DaiError OFFSET(7) NUMBITS(1) [], + /// Set to 1 if an error occurred in the LCI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index. + LciError OFFSET(8) NUMBITS(1) [], + /// Set to 1 if an integrity or consistency check times out.\nThis raises an fatal_check_error alert and is an unrecoverable error condition. + TimeoutError OFFSET(9) NUMBITS(1) [], + /// Set to 1 if the LFSR timer FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition. + LfsrFsmError OFFSET(10) NUMBITS(1) [], + /// Set to 1 if the scrambling datapath FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition. + ScramblingFsmError OFFSET(11) NUMBITS(1) [], + /// Set to 1 if the key derivation FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition. + KeyDerivFsmError OFFSET(12) NUMBITS(1) [], + /// This bit is set to 1 if a fatal bus integrity fault is detected.\nThis error triggers a fatal_bus_integ_error alert. + BusIntegError OFFSET(13) NUMBITS(1) [], + /// Set to 1 if the DAI is idle and ready to accept commands. + DailIdle OFFSET(14) NUMBITS(1) [], + /// Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending. + CheckPending OFFSET(15) NUMBITS(1) [], + ], + pub VendorTestReadLock [ + /// When cleared to 0, read access to the VENDOR_TEST partition is locked.\nWrite 0 to clear this bit. + ReadLock OFFSET(0) NUMBITS(1) [], + ], + pub ErrCodeRegT [ + /// No error condition has occurred. + NoError OFFSET(0) NUMBITS(1) [], + /// Returned if the OTP macr command was invalid or did not complete successfully + /// due to a macr malfunction. This error should never occur during normal operation and is not recoverable. + /// This error triggers an fatal_macr_error alert. + MacrError OFFSET(1) NUMBITS(1) [], + /// A correctable ECC error has occured during an OTP read operation.\nThe corresponding contrller automatically recovers frm this error when\nissuing a new command. + MacrEccCorrError OFFSET(2) NUMBITS(1) [], + /// An uncorrectable ECC error has occurred during an OTP read operation.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present this may be a sign that the device is malfunctioning.\nThis error triggers an fatal_macr_error alert. + MacrEccUncorrError OFFSET(3) NUMBITS(1) [], + /// This error is returned if a prgramming operation attempted to clear a bit that has previously been prgrammed to 1.\nThe corresponding contrller automatically recovers frm this error when issuing a new command.\n\nNote however that the affected OTP word may be left in an inconsistent state if this error occurs.\nThis can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a backgrund check).\n\nIt is important that SW ensures that each word is only written once, since this can render the device useless. + MacrWriteBlankError OFFSET(4) NUMBITS(1) [], + /// This error indicates that a locked memory region has been accessed.\nThe corresponding contrller automatically recovers frm this error when issuing a new command. + AccessError OFFSET(5) NUMBITS(1) [], + /// An ECC, integrity or consistency mismatch has been detected in the buffer registers.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_check_error alert. + CheckFailError OFFSET(6) NUMBITS(1) [], + /// The FSM of the corresponding contrller has reached an invalid state, or the FSM has\nbeen moved into a terminal error state due to an escalation action via lc_escalate_en_i.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present, this is a sign that the device has fallen victim to\nan invasive attack. This error triggers an fatal_check_error alert. + FsmStateError OFFSET(7) NUMBITS(1) [], + ], + } +} +pub mod regs { + //! Types that represent registers. + use tock_registers::register_structs; + register_structs! { + pub OtpCtrl { + (0x0 => pub interrupt_state: tock_registers::registers::ReadWrite), + (0x4 => pub otp_interrupt_enable: tock_registers::registers::ReadWrite), + (0x8 => pub interrupt_test: tock_registers::registers::WriteOnly), + (0xc => pub alert_test: tock_registers::registers::WriteOnly), + (0x10 => pub status: tock_registers::registers::ReadOnly), + (0x14 => pub err_code_rf_err_code_0: tock_registers::registers::ReadOnly), + (0x18 => pub err_code_rf_err_code_1: tock_registers::registers::ReadOnly), + (0x1c => pub err_code_rf_err_code_2: tock_registers::registers::ReadOnly), + (0x20 => pub err_code_rf_err_code_3: tock_registers::registers::ReadOnly), + (0x24 => pub err_code_rf_err_code_4: tock_registers::registers::ReadOnly), + (0x28 => pub err_code_rf_err_code_5: tock_registers::registers::ReadOnly), + (0x2c => pub err_code_rf_err_code_6: tock_registers::registers::ReadOnly), + (0x30 => pub err_code_rf_err_code_7: tock_registers::registers::ReadOnly), + (0x34 => pub err_code_rf_err_code_8: tock_registers::registers::ReadOnly), + (0x38 => pub direct_access_regwen: tock_registers::registers::ReadWrite), + (0x3c => pub direct_access_cmd: tock_registers::registers::WriteOnly), + (0x40 => pub direct_access_address: tock_registers::registers::ReadWrite), + (0x44 => pub dai_wdata_rf_direct_access_wdata_0: tock_registers::registers::ReadOnly), + (0x48 => pub dai_wdata_rf_direct_access_wdata_1: tock_registers::registers::ReadOnly), + (0x4c => pub dai_rdata_rf_direct_access_rdata_0: tock_registers::registers::ReadOnly), + (0x50 => pub dai_rdata_rf_direct_access_rdata_1: tock_registers::registers::ReadOnly), + (0x54 => pub check_trigger_regwen: tock_registers::registers::ReadWrite), + (0x58 => pub check_trigger: tock_registers::registers::WriteOnly), + (0x5c => pub check_regwen: tock_registers::registers::WriteOnly), + (0x60 => pub check_timeout: tock_registers::registers::ReadWrite), + (0x64 => pub integrity_check_period: tock_registers::registers::ReadWrite), + (0x68 => pub consistency_check_period: tock_registers::registers::ReadWrite), + (0x6c => pub vendor_test_read_lock: tock_registers::registers::ReadWrite), + (0x70 => pub non_secret_fuses_read_lock: tock_registers::registers::ReadWrite), + (0x74 => pub vendor_test_digest_digest_0: tock_registers::registers::ReadOnly), + (0x78 => pub vendor_test_digest_digest_1: tock_registers::registers::ReadOnly), + (0x7c => pub non_secret_fuses_digest_digest_0: tock_registers::registers::ReadOnly), + (0x80 => pub non_secret_fuses_digest_digest_1: tock_registers::registers::ReadOnly), + (0x84 => pub secret0_digest_digest_0: tock_registers::registers::ReadOnly), + (0x88 => pub secret0_digest_digest_1: tock_registers::registers::ReadOnly), + (0x8c => pub secret1_digest_digest_0: tock_registers::registers::ReadOnly), + (0x90 => pub secret1_digest_digest_1: tock_registers::registers::ReadOnly), + (0x94 => pub secret2_digest_digest_0: tock_registers::registers::ReadOnly), + (0x98 => pub secret2_digest_digest_1: tock_registers::registers::ReadOnly), + (0x9c => pub secret3_digest_digest_0: tock_registers::registers::ReadOnly), + (0xa0 => pub secret3_digest_digest_1: tock_registers::registers::ReadOnly), + (0xa4 => pub csr0: tock_registers::registers::ReadWrite), + (0xa8 => pub csr1: tock_registers::registers::ReadWrite), + (0xac => pub csr2: tock_registers::registers::ReadWrite), + (0xb0 => pub csr3: tock_registers::registers::ReadWrite), + (0xb4 => pub csr4: tock_registers::registers::ReadWrite), + (0xb8 => pub csr5: tock_registers::registers::ReadWrite), + (0xbc => pub csr6: tock_registers::registers::ReadWrite), + (0xc0 => pub csr7: tock_registers::registers::ReadOnly), + (0xc4 => @END), + } + } +} diff --git a/registers/generated-firmware/src/sha512_acc.rs b/registers/generated-firmware/src/sha512_acc.rs index 67f3c4a..45e17be 100644 --- a/registers/generated-firmware/src/sha512_acc.rs +++ b/registers/generated-firmware/src/sha512_acc.rs @@ -112,28 +112,28 @@ pub mod regs { (0x20 => pub digest: [tock_registers::registers::ReadOnly; 16]), (0x60 => pub control: tock_registers::registers::ReadWrite), (0x64 => _reserved0), - (0x800 => pub global_intr_en_r: tock_registers::registers::ReadWrite), - (0x804 => pub error_intr_en_r: tock_registers::registers::ReadWrite), - (0x808 => pub notif_intr_en_r: tock_registers::registers::ReadWrite), - (0x80c => pub error_global_intr_r: tock_registers::registers::ReadOnly), - (0x810 => pub notif_global_intr_r: tock_registers::registers::ReadOnly), - (0x814 => pub error_internal_intr_r: tock_registers::registers::ReadWrite), - (0x818 => pub notif_internal_intr_r: tock_registers::registers::ReadWrite), - (0x81c => pub error_intr_trig_r: tock_registers::registers::ReadWrite), - (0x820 => pub notif_intr_trig_r: tock_registers::registers::ReadWrite), + (0x800 => pub intr_block_rf_global_intr_en_r: tock_registers::registers::ReadWrite), + (0x804 => pub intr_block_rf_error_intr_en_r: tock_registers::registers::ReadWrite), + (0x808 => pub intr_block_rf_notif_intr_en_r: tock_registers::registers::ReadWrite), + (0x80c => pub intr_block_rf_error_global_intr_r: tock_registers::registers::ReadOnly), + (0x810 => pub intr_block_rf_notif_global_intr_r: tock_registers::registers::ReadOnly), + (0x814 => pub intr_block_rf_error_internal_intr_r: tock_registers::registers::ReadWrite), + (0x818 => pub intr_block_rf_notif_internal_intr_r: tock_registers::registers::ReadWrite), + (0x81c => pub intr_block_rf_error_intr_trig_r: tock_registers::registers::ReadWrite), + (0x820 => pub intr_block_rf_notif_intr_trig_r: tock_registers::registers::ReadWrite), (0x824 => _reserved1), - (0x900 => pub error0_intr_count_r: tock_registers::registers::ReadWrite), - (0x904 => pub error1_intr_count_r: tock_registers::registers::ReadWrite), - (0x908 => pub error2_intr_count_r: tock_registers::registers::ReadWrite), - (0x90c => pub error3_intr_count_r: tock_registers::registers::ReadWrite), + (0x900 => pub intr_block_rf_error0_intr_count_r: tock_registers::registers::ReadWrite), + (0x904 => pub intr_block_rf_error1_intr_count_r: tock_registers::registers::ReadWrite), + (0x908 => pub intr_block_rf_error2_intr_count_r: tock_registers::registers::ReadWrite), + (0x90c => pub intr_block_rf_error3_intr_count_r: tock_registers::registers::ReadWrite), (0x910 => _reserved2), - (0x980 => pub notif_cmd_done_intr_count_r: tock_registers::registers::ReadWrite), + (0x980 => pub intr_block_rf_notif_cmd_done_intr_count_r: tock_registers::registers::ReadWrite), (0x984 => _reserved3), - (0xa00 => pub error0_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa04 => pub error1_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa08 => pub error2_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa0c => pub error3_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa10 => pub notif_cmd_done_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa00 => pub intr_block_rf_error0_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa04 => pub intr_block_rf_error1_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa08 => pub intr_block_rf_error2_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa0c => pub intr_block_rf_error3_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa10 => pub intr_block_rf_notif_cmd_done_intr_count_incr_r: tock_registers::registers::ReadOnly), (0xa14 => @END), } } diff --git a/registers/generated-firmware/src/soc_ifc.rs b/registers/generated-firmware/src/soc_ifc.rs index 7f1a523..47d954d 100644 --- a/registers/generated-firmware/src/soc_ifc.rs +++ b/registers/generated-firmware/src/soc_ifc.rs @@ -346,46 +346,46 @@ pub mod regs { (0x648 => pub internal_rv_mtimecmp_l: tock_registers::registers::ReadWrite), (0x64c => pub internal_rv_mtimecmp_h: tock_registers::registers::ReadWrite), (0x650 => _reserved4), - (0x800 => pub global_intr_en_r: tock_registers::registers::ReadWrite), - (0x804 => pub error_intr_en_r: tock_registers::registers::ReadWrite), - (0x808 => pub notif_intr_en_r: tock_registers::registers::ReadWrite), - (0x80c => pub error_global_intr_r: tock_registers::registers::ReadOnly), - (0x810 => pub notif_global_intr_r: tock_registers::registers::ReadOnly), - (0x814 => pub error_internal_intr_r: tock_registers::registers::ReadWrite), - (0x818 => pub notif_internal_intr_r: tock_registers::registers::ReadWrite), - (0x81c => pub error_intr_trig_r: tock_registers::registers::ReadWrite), - (0x820 => pub notif_intr_trig_r: tock_registers::registers::ReadWrite), + (0x800 => pub intr_block_rf_global_intr_en_r: tock_registers::registers::ReadWrite), + (0x804 => pub intr_block_rf_error_intr_en_r: tock_registers::registers::ReadWrite), + (0x808 => pub intr_block_rf_notif_intr_en_r: tock_registers::registers::ReadWrite), + (0x80c => pub intr_block_rf_error_global_intr_r: tock_registers::registers::ReadOnly), + (0x810 => pub intr_block_rf_notif_global_intr_r: tock_registers::registers::ReadOnly), + (0x814 => pub intr_block_rf_error_internal_intr_r: tock_registers::registers::ReadWrite), + (0x818 => pub intr_block_rf_notif_internal_intr_r: tock_registers::registers::ReadWrite), + (0x81c => pub intr_block_rf_error_intr_trig_r: tock_registers::registers::ReadWrite), + (0x820 => pub intr_block_rf_notif_intr_trig_r: tock_registers::registers::ReadWrite), (0x824 => _reserved5), - (0x900 => pub error_internal_intr_count_r: tock_registers::registers::ReadWrite), - (0x904 => pub error_inv_dev_intr_count_r: tock_registers::registers::ReadWrite), - (0x908 => pub error_cmd_fail_intr_count_r: tock_registers::registers::ReadWrite), - (0x90c => pub error_bad_fuse_intr_count_r: tock_registers::registers::ReadWrite), - (0x910 => pub error_iccm_blocked_intr_count_r: tock_registers::registers::ReadWrite), - (0x914 => pub error_mbox_ecc_unc_intr_count_r: tock_registers::registers::ReadWrite), - (0x918 => pub error_wdt_timer1_timeout_intr_count_r: tock_registers::registers::ReadWrite), - (0x91c => pub error_wdt_timer2_timeout_intr_count_r: tock_registers::registers::ReadWrite), + (0x900 => pub intr_block_rf_error_internal_intr_count_r: tock_registers::registers::ReadWrite), + (0x904 => pub intr_block_rf_error_inv_dev_intr_count_r: tock_registers::registers::ReadWrite), + (0x908 => pub intr_block_rf_error_cmd_fail_intr_count_r: tock_registers::registers::ReadWrite), + (0x90c => pub intr_block_rf_error_bad_fuse_intr_count_r: tock_registers::registers::ReadWrite), + (0x910 => pub intr_block_rf_error_iccm_blocked_intr_count_r: tock_registers::registers::ReadWrite), + (0x914 => pub intr_block_rf_error_mbox_ecc_unc_intr_count_r: tock_registers::registers::ReadWrite), + (0x918 => pub intr_block_rf_error_wdt_timer1_timeout_intr_count_r: tock_registers::registers::ReadWrite), + (0x91c => pub intr_block_rf_error_wdt_timer2_timeout_intr_count_r: tock_registers::registers::ReadWrite), (0x920 => _reserved6), - (0x980 => pub notif_cmd_avail_intr_count_r: tock_registers::registers::ReadWrite), - (0x984 => pub notif_mbox_ecc_cor_intr_count_r: tock_registers::registers::ReadWrite), - (0x988 => pub notif_debug_locked_intr_count_r: tock_registers::registers::ReadWrite), - (0x98c => pub notif_scan_mode_intr_count_r: tock_registers::registers::ReadWrite), - (0x990 => pub notif_soc_req_lock_intr_count_r: tock_registers::registers::ReadWrite), - (0x994 => pub notif_gen_in_toggle_intr_count_r: tock_registers::registers::ReadWrite), + (0x980 => pub intr_block_rf_notif_cmd_avail_intr_count_r: tock_registers::registers::ReadWrite), + (0x984 => pub intr_block_rf_notif_mbox_ecc_cor_intr_count_r: tock_registers::registers::ReadWrite), + (0x988 => pub intr_block_rf_notif_debug_locked_intr_count_r: tock_registers::registers::ReadWrite), + (0x98c => pub intr_block_rf_notif_scan_mode_intr_count_r: tock_registers::registers::ReadWrite), + (0x990 => pub intr_block_rf_notif_soc_req_lock_intr_count_r: tock_registers::registers::ReadWrite), + (0x994 => pub intr_block_rf_notif_gen_in_toggle_intr_count_r: tock_registers::registers::ReadWrite), (0x998 => _reserved7), - (0xa00 => pub error_internal_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa04 => pub error_inv_dev_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa08 => pub error_cmd_fail_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa0c => pub error_bad_fuse_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa10 => pub error_iccm_blocked_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa14 => pub error_mbox_ecc_unc_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa18 => pub error_wdt_timer1_timeout_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa1c => pub error_wdt_timer2_timeout_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa20 => pub notif_cmd_avail_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa24 => pub notif_mbox_ecc_cor_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa28 => pub notif_debug_locked_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa2c => pub notif_scan_mode_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa30 => pub notif_soc_req_lock_intr_count_incr_r: tock_registers::registers::ReadOnly), - (0xa34 => pub notif_gen_in_toggle_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa00 => pub intr_block_rf_error_internal_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa04 => pub intr_block_rf_error_inv_dev_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa08 => pub intr_block_rf_error_cmd_fail_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa0c => pub intr_block_rf_error_bad_fuse_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa10 => pub intr_block_rf_error_iccm_blocked_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa14 => pub intr_block_rf_error_mbox_ecc_unc_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa18 => pub intr_block_rf_error_wdt_timer1_timeout_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa1c => pub intr_block_rf_error_wdt_timer2_timeout_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa20 => pub intr_block_rf_notif_cmd_avail_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa24 => pub intr_block_rf_notif_mbox_ecc_cor_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa28 => pub intr_block_rf_notif_debug_locked_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa2c => pub intr_block_rf_notif_scan_mode_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa30 => pub intr_block_rf_notif_soc_req_lock_intr_count_incr_r: tock_registers::registers::ReadOnly), + (0xa34 => pub intr_block_rf_notif_gen_in_toggle_intr_count_incr_r: tock_registers::registers::ReadOnly), (0xa38 => @END), } } diff --git a/registers/generator/src/codegen.rs b/registers/generator/src/codegen.rs index e88e59b..d54e09a 100644 --- a/registers/generator/src/codegen.rs +++ b/registers/generator/src/codegen.rs @@ -288,11 +288,20 @@ fn format_comment(comment: &str, indent: usize) -> String { result } -fn flatten_registers(block: &RegisterBlock, offset: u64) -> Vec { +fn flatten_registers( + block: &RegisterBlock, + offset: u64, + prefix_name: &str, + level: usize, +) -> Vec { let mut registers = Vec::new(); for reg in block.registers.iter() { assert!(reg.ty.name.is_some() || has_single_32_bit_field(®.ty)); let mut r = reg.as_ref().clone(); + // don't add a prefix to the top level as that would be redundant + if level > 0 && !prefix_name.is_empty() { + r.name = format!("{}_{}", prefix_name, r.name); + } r.offset += offset; registers.push(r); } @@ -300,6 +309,8 @@ fn flatten_registers(block: &RegisterBlock, offset: u64) -> Vec { registers.extend(flatten_registers( sub_block.block(), offset + sub_block.start_offset(), + &sub_block.block().name, + level + 1, )); } registers.sort_by_key(|r| r.offset); @@ -308,7 +319,7 @@ fn flatten_registers(block: &RegisterBlock, offset: u64) -> Vec { fn generate_reg_structs(crate_prefix: &str, block: &RegisterBlock) -> String { let name = &block.name; - let registers = flatten_registers(block, 0); + let registers = flatten_registers(block, 0, "", 0); let name = camel_case(name); let mut tokens = format!("register_structs! {{\n pub {name} {{\n"); diff --git a/runtime/i3c/src/core.rs b/runtime/i3c/src/core.rs index 5629b22..f304788 100644 --- a/runtime/i3c/src/core.rs +++ b/runtime/i3c/src/core.rs @@ -127,7 +127,7 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { } pub fn configure(&self, device_characteristic: u8) { - self.registers.stby_cr_device_char.modify( + self.registers.stdby_ctrl_mode_stby_cr_device_char.modify( StbyCrDeviceChar::Dcr.val(device_characteristic as u32) + StbyCrDeviceChar::BcrVar.val(Self::BCR), ); @@ -138,12 +138,12 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { // https://chipsalliance.github.io/i3c-core/initialization.html // Verify the value of the HCI_VERSION register at the I3CBase address. The controller is compliant with MIPI HCI v1.2 and therefore the HCI_VERSION should read 0x120 - if self.registers.hci_version.get() != 0x120 { + if self.registers.i3c_base_hci_version.get() != 0x120 { panic!("HCI version is not 0x120"); } if !self .registers - .stby_cr_capabilities + .stdby_ctrl_mode_stby_cr_capabilities .is_set(StbyCrCapabilities::TargetXactSupport) { panic!("I3C target transaction support is not enabled"); @@ -152,25 +152,25 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { // Evaluate RING_HEADERS_SECTION_OFFSET, the SECTION_OFFSET should read 0x0 as this controller doesn’t support the DMA mode let rhso = self .registers - .ring_headers_section_offset + .i3c_base_ring_headers_section_offset .read(RingHeadersSectionOffset::SectionOffset); if rhso != 0 { panic!("RING_HEADERS_SECTION_OFFSET is not 0"); } // initialize timing registers - self.registers.t_r_reg.set(0x2); - self.registers.t_hd_dat_reg.set(0xa); - self.registers.t_su_dat_reg.set(0xa); + self.registers.soc_mgmt_if_t_r_reg.set(0x2); + self.registers.soc_mgmt_if_t_hd_dat_reg.set(0xa); + self.registers.soc_mgmt_if_t_su_dat_reg.set(0xa); // Setup the threshold for the HCI queues (in the internal/private software data structures): - self.registers.queue_thld_ctrl.modify( + self.registers.piocontrol_queue_thld_ctrl.modify( QueueThldCtrl::CmdEmptyBufThld.val(0) + QueueThldCtrl::RespBufThld.val(1) + QueueThldCtrl::IbiStatusThld.val(1), ); - self.registers.stby_cr_control.modify( + self.registers.stdby_ctrl_mode_stby_cr_control.modify( StbyCrControl::StbyCrEnableInit::SET // enable the standby controller + StbyCrControl::TargetXactEnable::SET // enable Target Transaction Interface + StbyCrControl::DaaEntdaaEnable::SET // enable dynamic address assignment @@ -180,7 +180,7 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { ); // set TTI queue thresholds - self.registers.tti_queue_thld_ctrl.modify( + self.registers.tti_tti_queue_thld_ctrl.modify( TtiQueueThldCtrl::IbiThld.val(1) + TtiQueueThldCtrl::RxDescThld.val(1) + TtiQueueThldCtrl::TxDescThld.val(1), @@ -188,12 +188,12 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { // enable the PHY connection to the bus self.registers - .hc_control + .i3c_base_hc_control .modify(ModeSelector::SET + BusEnable::SET); } pub fn enable_interrupts(&self) { - self.registers.interrupt_enable.modify( + self.registers.tti_interrupt_enable.modify( InterruptEnable::IbiThldStatEn::SET + InterruptEnable::RxDescThldStatEn::SET + InterruptEnable::TxDescThldStatEn::SET @@ -203,7 +203,7 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { } pub fn disable_interrupts(&self) { - self.registers.interrupt_enable.modify( + self.registers.tti_interrupt_enable.modify( InterruptEnable::IbiThldStatEn::CLEAR + InterruptEnable::RxDescThldStatEn::CLEAR + InterruptEnable::TxDescThldStatEn::CLEAR @@ -213,14 +213,14 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { } pub fn handle_interrupt(&self, _error: bool) { - let tti_interrupts = self.registers.interrupt_status.extract(); + let tti_interrupts = self.registers.tti_interrupt_status.extract(); if tti_interrupts.get() != 0 { // Bus error occurred if tti_interrupts.read(InterruptStatus::TransferErrStat) != 0 { self.transfer_error(); // clear the interrupt self.registers - .interrupt_status + .tti_interrupt_status .write(InterruptStatus::TransferErrStat::SET); } // Bus aborted transaction @@ -228,42 +228,42 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { self.transfer_error(); // clear the interrupt self.registers - .interrupt_status + .tti_interrupt_status .write(InterruptStatus::TransferAbortStat::SET); } // TTI IBI Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI IBI Queue is >= the value defined in `TTI_IBI_THLD` if tti_interrupts.read(InterruptStatus::IbiThldStat) != 0 { debug!("Ignoring I3C IBI threshold interrupt"); self.registers - .interrupt_enable + .tti_interrupt_enable .modify(InterruptEnable::IbiThldStatEn::CLEAR); } // TTI RX Descriptor Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI RX Descriptor Queue is >= the value defined in `TTI_RX_DESC_THLD` if tti_interrupts.read(InterruptStatus::RxDescThldStat) != 0 { debug!("Ignoring I3C RX descriptor buffer threshold interrupt"); self.registers - .interrupt_enable + .tti_interrupt_enable .modify(InterruptEnable::RxDescThldStatEn::CLEAR); } // TTI TX Descriptor Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI TX Descriptor Queue is >= the value defined in `TTI_TX_DESC_THLD` if tti_interrupts.read(InterruptStatus::TxDescThldStat) != 0 { debug!("Ignoring I3C TX descriptor buffer threshold interrupt"); self.registers - .interrupt_enable + .tti_interrupt_enable .modify(InterruptEnable::TxDescThldStatEn::CLEAR); } // TTI RX Data Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of entries in the TTI RX Data Queue is >= the value defined in `TTI_RX_DATA_THLD` if tti_interrupts.read(InterruptStatus::RxDataThldStat) != 0 { debug!("Ignoring I3C RX data buffer buffer threshold interrupt"); self.registers - .interrupt_enable + .tti_interrupt_enable .modify(InterruptEnable::RxDataThldStatEn::CLEAR); } // TTI TX Data Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI TX Data Queue is >= the value defined in TTI_TX_DATA_THLD if tti_interrupts.read(InterruptStatus::TxDataThldStat) != 0 { debug!("Ignoring I3C TX data buffer buffer threshold interrupt"); self.registers - .interrupt_enable + .tti_interrupt_enable .modify(InterruptEnable::TxDataThldStatEn::CLEAR); } // Pending Write was NACK’ed because the `TX_DESC_STAT` event was not handled in time @@ -271,7 +271,7 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { self.pending_write_nack(); // clear the interrupt self.registers - .interrupt_status + .tti_interrupt_status .write(InterruptStatus::TxDescTimeout::SET); } // Pending Read was NACK’ed because the `RX_DESC_STAT` event was not handled in time @@ -279,7 +279,7 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { self.pending_read_nack(); // clear the interrupt self.registers - .interrupt_status + .tti_interrupt_status .write(InterruptStatus::TxDescTimeout::SET); } // There is a pending Read Transaction on the I3C Bus. Software should write data to the TX Descriptor Queue and the TX Data Queue @@ -325,8 +325,8 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { let rx_buffer = self.rx_buffer.take().unwrap(); let mut buf_idx = self.rx_buffer_idx.get(); let buf_size = self.rx_buffer_size.get(); - let desc0 = self.registers.rx_desc_queue_port.get(); - let desc1 = self.registers.rx_desc_queue_port.get(); + let desc0 = self.registers.tti_rx_desc_queue_port.get(); + let desc1 = self.registers.tti_rx_desc_queue_port.get(); let desc = LocalRegisterCopy::::new( ((desc1 as u64) << 32) | (desc0 as u64), ); @@ -335,7 +335,7 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { // read everything let mut full = false; for i in (0..len.next_multiple_of(4)).step_by(4) { - let data = self.registers.rx_data_port0.get().to_le_bytes(); + let data = self.registers.tti_rx_data_port.get().to_le_bytes(); for j in 0..4 { if buf_idx >= buf_size { full = true; @@ -382,7 +382,9 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { let size = self.tx_buffer_size.replace(0); if idx < size { // TODO: get the correct structure of this descriptor - self.registers.tx_desc_queue_port.set((size - idx) as u32); + self.registers + .tti_tx_desc_queue_port + .set((size - idx) as u32); while idx < size { let mut bytes = [0; 4]; for i in 0..4.min(size - idx) { @@ -390,7 +392,7 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { idx += 1; } let word = u32::from_le_bytes(bytes); - self.registers.tx_data_port0.set(word); + self.registers.tti_tx_data_port.set(word); } } // we're done @@ -423,9 +425,9 @@ impl<'a, A: Alarm<'a>> I3CCore<'a, A> { fn send_ibi(&self, mdb: u8) { // TODO: it is unclear if we need to set anything else in the descriptor self.registers - .tti_ibi_port + .tti_tti_ibi_port .set(IbiDescriptor::DataLength.val(1).value); - self.registers.tti_ibi_port.set(mdb as u32); + self.registers.tti_tti_ibi_port.set(mdb as u32); } } @@ -472,13 +474,13 @@ impl<'a, A: Alarm<'a>> crate::hil::I3CTarget<'a> for I3CCore<'a, A> { fn get_device_info(&self) -> I3CTargetInfo { let dynamic_addr = if self .registers - .stby_cr_device_addr + .stdby_ctrl_mode_stby_cr_device_addr .read(StbyCrDeviceAddr::DynamicAddrValid) == 1 { Some( self.registers - .stby_cr_device_addr + .stdby_ctrl_mode_stby_cr_device_addr .read(StbyCrDeviceAddr::DynamicAddr) as u8, ) } else { @@ -486,13 +488,13 @@ impl<'a, A: Alarm<'a>> crate::hil::I3CTarget<'a> for I3CCore<'a, A> { }; let static_addr = if self .registers - .stby_cr_device_addr + .stdby_ctrl_mode_stby_cr_device_addr .read(StbyCrDeviceAddr::StaticAddrValid) == 1 { Some( self.registers - .stby_cr_device_addr + .stdby_ctrl_mode_stby_cr_device_addr .read(StbyCrDeviceAddr::StaticAddr) as u8, ) } else { diff --git a/xtask/src/registers.rs b/xtask/src/registers.rs index a7e5c16..0452324 100644 --- a/xtask/src/registers.rs +++ b/xtask/src/registers.rs @@ -54,6 +54,9 @@ pub(crate) fn autogen( "hw/caliptra-ss/src/integration/rtl/soc_address_map.rdl", "hw/el2_pic_ctrl.rdl", "hw/flash_ctrl.rdl", + "hw/entropy_src.rdl", + "hw/otp_ctrl.rdl", + "hw/mcu.rdl", ]; let mut rdl_files: Vec = rdl_files.iter().map(|s| PROJECT_ROOT.join(s)).collect(); rdl_files.extend_from_slice(extra_files); @@ -82,7 +85,7 @@ pub(crate) fn autogen( } // eliminate duplicate type names - let patches = vec![ + let patches = [ ( PROJECT_ROOT.join( "hw/caliptra-ss/third_party/i3c-core/src/rdl/target_transaction_interface.rdl", @@ -118,6 +121,16 @@ pub(crate) fn autogen( "RESET_CONTROL", "TTI_RESET_CONTROL", ), + ( + PROJECT_ROOT.join("hw/entropy_src.rdl"), + "INTERRUPT_ENABLE", + "ENTROPY_INTERRUPT_ENABLE", + ), + ( + PROJECT_ROOT.join("hw/otp_ctrl.rdl"), + "INTERRUPT_ENABLE", + "OTP_INTERRUPT_ENABLE", + ), ]; for rdl in rdl_files.iter() { @@ -170,9 +183,8 @@ pub(crate) fn autogen( let scope = scope.as_parent(); let addrmap = scope.lookup_typedef("soc").unwrap(); - let addrmap2 = scope.lookup_typedef("el2_pic").unwrap(); - let addrmap3 = scope.lookup_typedef("flashctrl_dummy").unwrap(); - let mut scopes = vec![addrmap, addrmap2, addrmap3]; + let addrmap2 = scope.lookup_typedef("mcu").unwrap(); + let mut scopes = vec![addrmap, addrmap2]; if !extra_addrmap.is_empty() { let addrmap3 = scope.lookup_typedef("extra").unwrap(); scopes.push(addrmap3); @@ -226,6 +238,9 @@ fn generate_emulator_types( let mut validated_blocks = vec![]; for block in blocks.iter_mut() { + if block.name.starts_with("caliptra_") { + block.name = block.name[9..].to_string(); + } if block.name.ends_with("_reg") || block.name.ends_with("_csr") { block.name = block.name[0..block.name.len() - 4].to_string(); } @@ -749,6 +764,9 @@ fn generate_fw_registers( } let mut validated_blocks = vec![]; for mut block in blocks { + if block.name.starts_with("caliptra_") { + block.name = block.name[9..].to_string(); + } if block.name.ends_with("_reg") || block.name.ends_with("_csr") { block.name = block.name[0..block.name.len() - 4].to_string(); }