Adding cold reset, only verilator and FPGA supported

hw-model/src/lib.rs

@@ -243,7 +243,6 @@ fn trace_path_or_env(trace_path: Option<PathBuf>) -> Option<PathBuf> {
 }
 
 pub struct BootParams<'a> {
-    pub init_params: InitParams<'a>,
     pub fuses: Fuses,
     pub fw_image: Option<&'a [u8]>,
     pub initial_dbg_manuf_service_reg: u32,
@@ -256,7 +255,6 @@ pub struct BootParams<'a> {
 impl<'a> Default for BootParams<'a> {
     fn default() -> Self {
         Self {
-            init_params: Default::default(),
             fuses: Default::default(),
             fw_image: Default::default(),
             initial_dbg_manuf_service_reg: Default::default(),
@@ -597,10 +595,16 @@ pub trait HwModel {
 
     /// Toggle reset pins and wait for ready_for_fuses
     fn warm_reset(&mut self) {
-        // sw-emulator lacks support: https://github.com/chipsalliance/caliptra-sw/issues/540
+        // To be overridden by HwModel implementations that support this
         panic!("warm_reset unimplemented");
     }
 
+    /// Toggle reset/pwrgood pins and wait for ready_for_fuses
+    fn cold_reset(&mut self) {
+        // To be overridden by HwModel implementations that support this
+        panic!("cold_reset unimplemented");
+    }
+
     /// Returns true if the microcontroller has signalled that it is ready for
     /// firmware to be written to the mailbox. For RTL implementations, this
     /// should come via a caliptra_top wire rather than an APB register.
@@ -1704,4 +1708,24 @@ mod tests {
         });
         assert_eq!(resp, Err(ModelError::MailboxNoResponseData));
     }
+
+    #[test]
+    #[cfg(any(feature = "verilator", feature = "fpga_realtime"))]
+    pub fn test_cold_reset() {
+        let mut model = caliptra_hw_model::new(
+            InitParams {
+                rom: &gen_image_hi(),
+                ..Default::default()
+            },
+            BootParams::default(),
+        )
+        .unwrap();
+        model.step_until_output("hii").unwrap();
+
+        model.cold_reset();
+
+        model.boot(BootParams::default()).unwrap();
+
+        model.step_until_output("hii").unwrap();
+    }
 }

hw-model/src/model_fpga_realtime.rs

@@ -476,6 +476,16 @@ impl HwModel for ModelFpgaRealtime {
         while !self.is_ready_for_fuses() {}
     }
 
+    fn cold_reset(&mut self) {
+        // Toggle reset and pwrgood
+        self.set_cptra_rst_b(false);
+        self.set_cptra_pwrgood(false);
+        self.set_cptra_pwrgood(true);
+        self.set_cptra_rst_b(true);
+        // Wait for ready_for_fuses
+        while !self.is_ready_for_fuses() {}
+    }
+
     fn ready_for_fw(&self) -> bool {
         unsafe {
             GpioInput(

hw-model/src/model_verilated.rs

@@ -281,6 +281,27 @@ impl crate::HwModel for ModelVerilated {
         }
     }
 
+    fn cold_reset(&mut self) {
+        // Toggle reset pin
+        self.v.input.cptra_rst_b = false;
+        self.v.next_cycle_high(1);
+
+        // Toggle pwrgood pin
+        self.v.input.cptra_pwrgood = false;
+        self.v.next_cycle_high(1);
+
+        self.v.input.cptra_pwrgood = true;
+        self.v.next_cycle_high(1);
+
+        self.v.input.cptra_rst_b = true;
+        self.v.next_cycle_high(1);
+
+        // Wait for ready_for_fuses
+        while !self.v.output.ready_for_fuses {
+            self.v.next_cycle_high(1);
+        }
+    }
+
     fn ready_for_fw(&self) -> bool {
         self.v.output.ready_for_fw_push
     }