diff --git a/README.md b/README.md new file mode 100644 index 00000000..8d9e48f9 --- /dev/null +++ b/README.md @@ -0,0 +1,45 @@ +

+ + + +

+ +# F4PGA examples + +

+ + 'Doc' workflow status +

+ +This repository provides example FPGA designs that can be built using the F4PGA open source toolchain. +These examples target the Xilinx 7-Series and the QuickLogic EOS S3 devices. + +* Please refer to the [![](https://img.shields.io/website?longCache=true&style=flat-square&label=Documentation%20For%20Users&up_color=231f20&up_message=%E2%9E%9A&url=https%3A%2F%2Ff4pga-examples.readthedocs.io%2Fen%2Flatest%2Findex.html&labelColor=fff)](https://f4pga-examples.readthedocs.io) + for a proper guide on how to run these examples, as well as instructions on how to build and compile your own HDL designs using + the F4PGA toolchain. +* See [![](https://img.shields.io/website?longCache=true&style=flat-square&label=Documentation%20For%20Developers&up_color=white&up_message=%E2%9E%9A&url=https%3A%2F%2Ff4pga.readthedocs.io%2Fprojects%2Farch-defs%2Fen%2Flatest%2Findex.html&labelColor=231f20)](https://f4pga.readthedocs.io/projects/arch-defs/) + to contribute on the development of architecture support in F4PGA. + +The repository includes: + +* [xc7/](./xc7) and [eos-s3/](./eos-s3) - Examples for Xilinx 7-Series and EOS-S3 devices, including: + + * Verilog code + + * Pin constraints files + + * Timing constraints files + + * Makefiles for running the F4PGA toolchain + +* [docs/](./docs) - Guide on how to get started with F4PGA and build provided examples + +* [.github/](./.github) - Directory with CI configuration and scripts + +The examples provided in this repository are automatically built and tested in CI by extracting necessary code snippets +with [tuttest](https://github.com/antmicro/tuttest). diff --git a/README.rst b/README.rst deleted file mode 100644 index 4397d8aa..00000000 --- a/README.rst +++ /dev/null @@ -1,34 +0,0 @@ -F4PGA examples -============== - -.. image:: https://github.com/chipsalliance/f4pga-examples/workflows/doc-test/badge.svg?branch=master - :target: https://github.com/chipsalliance/f4pga-examples/actions - -.. image:: https://readthedocs.org/projects/f4pga-examples/badge/?version=latest - :target: https://f4pga-examples.readthedocs.io/en/latest/?badge=latest - :alt: Documentation Status - -This repository provides example FPGA designs that can be built using the F4PGA open source toolchain. -These examples target the Xilinx 7-Series and the QuickLogic EOS S3 devices. - -Please refer to the `project documentation `_ for a proper guide on how to run -these examples as well as instructions on how to build and compile your own HDL designs using the F4PGA toolchain. - -The repository includes: - -* `xc7/ <./xc7>`_ and `eos-s3/ <./eos-s3>`_ - Examples for Xilinx 7-Series and EOS-S3 devices, including: - - * Verilog code - - * Pin constraints files - - * Timing constraints files - - * Makefiles for running the F4PGA toolchain - -* `docs/ <./docs>`_ - Guide on how to get started with F4PGA and build provided examples - -* `.github/ <./.github>`_ - Directory with CI configuration and scripts - -The examples provided in this repository are automatically built and tested in CI by extracting necessary code snippets -with `tuttest `_.