s/SymbiFlow/F4PGA/

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>

xc7/litex_demo/README.rst

@@ -23,24 +23,24 @@ There are multiple CPU types supported, choose one from the below commands to ge
 .. code-block:: bash
    :name: example-litex_picorv32-a35t-group
 
-   ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_35 --variant a7-35 --build
+   ./src/litex/litex/boards/targets/arty.py --toolchain=f4pga --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_35 --variant a7-35 --build
 
 .. code-block:: bash
    :name: example-litex_picorv32-a100t-group
 
-   ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_100 --variant a7-100 --build
+   ./src/litex/litex/boards/targets/arty.py --toolchain=f4pga --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_100 --variant a7-100 --build
 
 **VexRiscv**
 
 .. code-block:: bash
    :name: example-litex_vexriscv-a35t-group
 
-   ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_35 --variant a7-35 --build
+   ./src/litex/litex/boards/targets/arty.py --toolchain=f4pga --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_35 --variant a7-35 --build
 
 .. code-block:: bash
    :name: example-litex_vexriscv-a100t-group
 
-   ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_100 --variant a7-100 --build
+   ./src/litex/litex/boards/targets/arty.py --toolchain=f4pga --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_100 --variant a7-100 --build
 
 Depending on which board and CPU-type you selected, the bitstream is loacted in:
 

xc7/litex_sata_demo/litesata.v

@@ -16863,7 +16863,7 @@ GTPE2_COMMON #(
 	// FIXME: The GTREFCLK1 needs to be used for this design.
 	// Vivado automatically swaps the input accordingly to the IBUFDS placement location
 	// and this is currently not doable in VPR. For the time being, we can just manually adjust it.
-	// https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2328
+	// https://github.com/chipsalliance/f4pga-arch-defs/issues/2328
 	.GTREFCLK1(a7litesataphy_gtrefclk0),
 	.PLL0LOCKEN(1'd1),
 	.PLL0PD(1'd0),
@@ -16880,7 +16880,7 @@ GTPE2_COMMON #(
 
 // FIXME: FDPE connected to the IBUFDS clk output need to be in the same clock region, otherwise resulting
 // 		  in an unroutable situation.
-// 		  https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2327
+// 		  https://github.com/chipsalliance/f4pga-arch-defs/issues/2327
 (* LOC="SLICE_X51Y227" *)
 FDPE #(
 	.INIT(1'd1)