Added test case for pack pattern annotation

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

tests/pack_pattern/README.rst

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+Pack pattern annotation example
++++++++++++++++++++++++++++++++
+
+VPR requires that connections between primitives that need to be packed together be annotated with pack patterns. Moreover, a single connection may have multiple pack pattern annotations.
+
+In V2X a pack pattern annotation can be specified for a given net using the `(* PACK *)` attribute. The value of the attribute can be either a single pack pattern name of a list of pack pattern names separated by semicolons.
+
+This example below contains a model of a logic block that has a LUT4 connected to a FF through a MUX. The mux allows to dynamically select whether the FF input is driven by the LUT or an external input.
+
+This is the HDL definition of the logic block
+
+|
+
+.. symbolator:: block.sim.v
+
+.. verilog-diagram:: block.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+
+|
+
+.. no-license:: block.sim.v
+   :language: verilog
+   :caption: tests/pack_pattern/block.sim.v
+
+There are two pack patterns one for LUT, MUX and FF packed together and one for MUX and FF without the LUT. The connection between the LUT and the MUX gets a single pack pattern annotation while the one between MUX and FF gets two annotations.
+
+The `(* PACK *)` attribute annotations result in pack_pattern tags to be added to the pb_type XML as it can be observed in the generated description below:
+
+.. literalinclude:: block.model.xml
+   :language: xml
+   :caption: block.model.xml
+
+.. literalinclude:: block.pb_type.xml
+   :language: xml
+   :caption: block.pb_type.xml

tests/pack_pattern/block.sim.v

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+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:     ISC
+ */
+
+`include "lut/lut.sim.v"
+`include "mux/mux.sim.v"
+`include "ff/ff.sim.v"
+
+module BLOCK (
+    input  wire       C,
+    input  wire [3:0] I,
+    input  wire       D,
+    input  wire       S,
+    output wire       Q
+);
+
+    // LUT
+    (* PACK="lut_mux_ff" *)
+    wire lut_out;
+
+    LUT lut_cell (
+        .I (I),
+        .O (lut_out)
+    );
+
+    // Mux
+    (* PACK="lut_mux_ff;mux_ff" *)
+    wire mux_out;
+
+    MUX mux_cell (
+        .I0 (lut_out),
+        .I1 (D),
+        .S  (S),
+        .O  (mux_out)
+    );
+
+    // FF
+    FF ff_cell (
+        .C  (C),
+        .D  (mux_out),
+        .Q  (Q)
+    );
+
+endmodule

tests/pack_pattern/ff/ff.pb_type.xml

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+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="FF" num_pb="1">
+  <blif_model>.subckt FF</blif_model>
+  <input name="C" num_pins="1"/>
+  <input name="D" num_pins="1"/>
+  <output name="Q" num_pins="1"/>
+</pb_type>

tests/pack_pattern/ff/ff.sim.v

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+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:     ISC
+ */
+
+module FF (
+    input  wire C,
+    input  wire D,
+    output reg  Q
+);
+
+    always @(posedge C)
+        Q <= D;
+
+endmodule

tests/pack_pattern/golden.pb_type.xml

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+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="BLOCK" num_pb="1">
+  <input name="C" num_pins="1"/>
+  <input name="D" num_pins="1"/>
+  <input name="I" num_pins="4"/>
+  <input name="S" num_pins="1"/>
+  <output name="Q" num_pins="1"/>
+  <pb_type name="ff_cell" num_pb="1">
+    <!--old_name FF-->
+    <xi:include href="ff/ff.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/>
+  </pb_type>
+  <pb_type name="lut_cell" num_pb="1">
+    <!--old_name LUT-->
+    <xi:include href="lut/lut.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/>
+  </pb_type>
+  <pb_type name="mux_cell" num_pb="1">
+    <!--old_name MUX-->
+    <xi:include href="mux/mux.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/>
+  </pb_type>
+  <interconnect>
+    <direct>
+      <port name="C" type="input"/>
+      <port from="ff_cell" name="C" type="output"/>
+    </direct>
+    <direct>
+      <port from="mux_cell" name="O" type="input"/>
+      <port from="ff_cell" name="D" type="output"/>
+      <pack_pattern name="lut_mux_ff" type="pack">
+        <port from="mux_cell" name="O" type="input"/>
+        <port from="ff_cell" name="D" type="output"/>
+      </pack_pattern>
+      <pack_pattern name="mux_ff" type="pack">
+        <port from="mux_cell" name="O" type="input"/>
+        <port from="ff_cell" name="D" type="output"/>
+      </pack_pattern>
+    </direct>
+    <direct>
+      <port from="ff_cell" name="Q" type="input"/>
+      <port name="Q" type="output"/>
+    </direct>
+    <direct>
+      <port name="I[0]" type="input"/>
+      <port from="lut_cell" name="I[0]" type="output"/>
+    </direct>
+    <direct>
+      <port name="I[1]" type="input"/>
+      <port from="lut_cell" name="I[1]" type="output"/>
+    </direct>
+    <direct>
+      <port name="I[2]" type="input"/>
+      <port from="lut_cell" name="I[2]" type="output"/>
+    </direct>
+    <direct>
+      <port name="I[3]" type="input"/>
+      <port from="lut_cell" name="I[3]" type="output"/>
+    </direct>
+    <direct>
+      <port from="lut_cell" name="O" type="input"/>
+      <port from="mux_cell" name="I0" type="output"/>
+      <pack_pattern name="lut_mux_ff" type="pack">
+        <port from="lut_cell" name="O" type="input"/>
+        <port from="mux_cell" name="I0" type="output"/>
+      </pack_pattern>
+    </direct>
+    <direct>
+      <port name="D" type="input"/>
+      <port from="mux_cell" name="I1" type="output"/>
+    </direct>
+    <direct>
+      <port name="S" type="input"/>
+      <port from="mux_cell" name="S" type="output"/>
+    </direct>
+  </interconnect>
+</pb_type>

tests/pack_pattern/lut/lut.pb_type.xml

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+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="LUT" num_pb="1">
+  <blif_model>.subckt LUT</blif_model>
+  <input name="I" num_pins="4"/>
+  <output name="O" num_pins="1"/>
+</pb_type>

tests/pack_pattern/lut/lut.sim.v

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+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:     ISC
+ */
+
+module LUT (
+    input  wire [3:0] I,
+    output wire       O
+);
+
+    parameter [15:0] INIT = 'd0;
+
+    assign O = INIT[i];
+
+endmodule

tests/pack_pattern/mux/mux.pb_type.xml

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+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="MUX" num_pb="1">
+  <blif_model>.subckt MUX</blif_model>
+  <input name="I0" num_pins="1"/>
+  <input name="I1" num_pins="1"/>
+  <input name="S" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+</pb_type>

tests/pack_pattern/mux/mux.sim.v

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+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:     ISC
+ */
+
+module MUX (
+    input  wire I0,
+    input  wire I1,
+    input  wire S,
+    output wire O
+);
+
+    assign O = S ? I1 : I0;
+
+endmodule