Skip to content
View cla7aye15I4nd's full-sized avatar
INFP
INFP

Highlights

  • Pro

Organizations

@qilingframework

Block or report cla7aye15I4nd

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
cla7aye15I4nd/README.md

Hi there 👋, this is dataisland (CV).

Bachelor@Shang Hai Jiao Tong University

PhD@NorthWestern University

Security Engineer, Qiling Core Developer, CTF Player, Open-source enthusiast.

  • Compiler
  • Linux Kernel
  • Symbolic Execution
  • Large Language Model
  • Microcontroller Emulation
  • Reverse Engineering.

Pinned Loading

  1. CAMP CAMP Public

    CAMP: Compiler and Allocator-based Heap Memory Protection (USENIX Security 2024) ✨ Please give a star to https://github.com/cla7aye15I4nd/shadowbound next door! 🌟😊

    C++ 35 2

  2. shadowbound shadowbound Public

    ShadowBound: Efficient Memory Protection through Advanced Metadata Management and Customized Compiler Optimization (USENIX Security 2024) ✨ Please give a star to https://github.com/cla7aye15I4nd/CA…

    C++ 22 1

  3. sherdencooper/GPTFuzz sherdencooper/GPTFuzz Public

    Official repo for GPTFUZZER : Red Teaming Large Language Models with Auto-Generated Jailbreak Prompts

    Python 397 50

  4. waifu4x waifu4x Public

    2019 PPCA course project - Anime Super-Resolution

    Python 27 1

  5. awesome-mcu awesome-mcu Public

    Some learning materials, notes and scripts about the programming and security of microcontroller.

    Python 11 1

  6. trivial-riscv-cpu trivial-riscv-cpu Public

    A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.

    Verilog 13 1