Add ok signal to outputs of Sgmii

clash-lang · Jun 30, 2024 · 4c506e3 · 4c506e3
1 parent 7f274b5
commit 4c506e3
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/clash-cores/src/Clash/Cores/Sgmii.hs b/clash-cores/src/Clash/Cores/Sgmii.hs
@@ -28,7 +28,7 @@ sgmiiCdc ::
   Signal txDom Bool ->
   Signal txDom (BitVector 8) ->
   Signal rxDom (BitVector 10) ->
-  ( Signal rxDom (Bool, Bool, BitVector 8, BitVector 8, BitVector 10)
+  ( Signal rxDom (Bool, Bool, BitVector 8, BitVector 8, BitVector 10, Bool)
   , Signal txDom (BitVector 10)
   )
 sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 =
@@ -38,6 +38,7 @@ sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 =
       , exposeClockResetEnable regMaybe rxClk rxRst enableGen 0 dw4
       , fromDw . head <$> dw2
       , cg2
+      , ok
       )
   , cg4
   )
@@ -69,7 +70,7 @@ sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 =
    where
     sync' = exposeClockResetEnable sync
 
-  (cg2, _) = unbundle $ bitSlip' rxClk rxRst enableGen cg1
+  (cg2, ok) = unbundle $ bitSlip' rxClk rxRst enableGen cg1
    where
     bitSlip' = exposeClockResetEnable bitSlip
 

diff --git a/clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs b/clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs
@@ -56,7 +56,7 @@ bitSlipO ::
   (BitSlipState 10, BitVector 10, Bool)
 bitSlipO self@BSFail{..} = out
  where
-  out = (self, resize $ rotateR _s (10 - fromEnum (last _ns)), False)
+  out = (self, resize _s, False)
 bitSlipO self@BSOk{..} = out
  where
   out = (self, resize $ rotateR _s (10 - fromEnum _n), True)