From 4c506e3a201d17f512a13d3ebe94b009200f3456 Mon Sep 17 00:00:00 2001 From: Jasper Vinkenvleugel Date: Sun, 30 Jun 2024 14:27:36 +0200 Subject: [PATCH] Add ok signal to outputs of Sgmii --- clash-cores/src/Clash/Cores/Sgmii.hs | 5 +++-- clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/clash-cores/src/Clash/Cores/Sgmii.hs b/clash-cores/src/Clash/Cores/Sgmii.hs index 2e0372eac2..4825edfd21 100644 --- a/clash-cores/src/Clash/Cores/Sgmii.hs +++ b/clash-cores/src/Clash/Cores/Sgmii.hs @@ -28,7 +28,7 @@ sgmiiCdc :: Signal txDom Bool -> Signal txDom (BitVector 8) -> Signal rxDom (BitVector 10) -> - ( Signal rxDom (Bool, Bool, BitVector 8, BitVector 8, BitVector 10) + ( Signal rxDom (Bool, Bool, BitVector 8, BitVector 8, BitVector 10, Bool) , Signal txDom (BitVector 10) ) sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 = @@ -38,6 +38,7 @@ sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 = , exposeClockResetEnable regMaybe rxClk rxRst enableGen 0 dw4 , fromDw . head <$> dw2 , cg2 + , ok ) , cg4 ) @@ -69,7 +70,7 @@ sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 = where sync' = exposeClockResetEnable sync - (cg2, _) = unbundle $ bitSlip' rxClk rxRst enableGen cg1 + (cg2, ok) = unbundle $ bitSlip' rxClk rxRst enableGen cg1 where bitSlip' = exposeClockResetEnable bitSlip diff --git a/clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs b/clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs index da2d2c8222..3bad9459d1 100644 --- a/clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs +++ b/clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs @@ -56,7 +56,7 @@ bitSlipO :: (BitSlipState 10, BitVector 10, Bool) bitSlipO self@BSFail{..} = out where - out = (self, resize $ rotateR _s (10 - fromEnum (last _ns)), False) + out = (self, resize _s, False) bitSlipO self@BSOk{..} = out where out = (self, resize $ rotateR _s (10 - fromEnum _n), True)