diff --git a/clash-cores/test/Test/Cores/Sgmii/BitSlip.hs b/clash-cores/test/Test/Cores/Sgmii/BitSlip.hs
index 8c8c9b5c75..c146600be3 100644
--- a/clash-cores/test/Test/Cores/Sgmii/BitSlip.hs
+++ b/clash-cores/test/Test/Cores/Sgmii/BitSlip.hs
@@ -31,7 +31,7 @@ bitSlipSim cg =
       (cg, pure Ok)
 
 -- | Check that if 'bitSlip' moves into 'BSOk', the index is non-zero as it
---   needs to be over code group boundaries due to 'codeGroupOk'
+--   needs to be over code group boundaries due to 'checkBitSequence'
 prop_bitSlipNoBSOk :: H.Property
 prop_bitSlipNoBSOk = H.property $ do
   simDuration <- H.forAll (Gen.integral (Range.linear 1 100))
@@ -40,7 +40,7 @@ prop_bitSlipNoBSOk = H.property $ do
     H.forAll
       ( Gen.list
           (Range.singleton simDuration)
-          (Gen.filter codeGroupOk genDefinedBitVector)
+          (Gen.filter checkBitSequence genDefinedBitVector)
       )
   let simOut =
         map f $
diff --git a/clash-cores/test/Test/Cores/Sgmii/Sync.hs b/clash-cores/test/Test/Cores/Sgmii/Sync.hs
index f41e0a98a6..f9ba87a934 100644
--- a/clash-cores/test/Test/Cores/Sgmii/Sync.hs
+++ b/clash-cores/test/Test/Cores/Sgmii/Sync.hs
@@ -26,7 +26,7 @@ prop_syncNotOk = H.property $ do
     H.forAll
       ( Gen.list
           (Range.singleton simDuration)
-          (Gen.filter codeGroupOk genDefinedBitVector)
+          (Gen.filter checkBitSequence genDefinedBitVector)
       )
   let simOut =
         map f $
@@ -46,7 +46,7 @@ prop_syncPropagateDw = H.property $ do
     H.forAll
       ( Gen.list
           (Range.singleton simDuration)
-          (Gen.filter codeGroupOk genDefinedBitVector)
+          (Gen.filter checkBitSequence genDefinedBitVector)
       )
   let delaySamples = 5