Remove clash-cores from clash-testsuite (#2793)

clash-lang · Aug 26, 2024 · b14ff0e · b14ff0e
1 parent 280905d
commit b14ff0e
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Showing 33 changed files with 1 addition and 3,694 deletions.
diff --git a/nix/overlay.nix b/nix/overlay.nix
@@ -194,7 +194,7 @@ let
               "clash-testsuite"
               ../tests
               "--flag workaround-ghc-mmap-crash" {
-              inherit (hfinal) clash-cores clash-ghc clash-lib clash-prelude;
+              inherit (hfinal) clash-ghc clash-lib clash-prelude;
             };
         in
         unmodified.overrideAttrs (old: {

diff --git a/tests/Main.hs b/tests/Main.hs
@@ -192,40 +192,6 @@ runClashTest = defaultMain $ clashTestRoot
           , expectClashFail=Just (def, "Template function for returned False")
           }
         ]
-      , clashTestGroup "Cores"
-        [ clashTestGroup "Xilinx"
-          [ clashTestGroup "VIO"
-            [ runTest "DuplicateOutputNames" def{
-                hdlTargets=[VHDL]
-              , expectClashFail=Just (def, "Tried create a signal called 'a', but identifier generation returned")
-              }
-            , runTest "DuplicateInputNames" def{
-                hdlTargets=[VHDL]
-              , expectClashFail=Just (def, "Tried create a signal called 'a', but identifier generation returned")
-              }
-            , runTest "DuplicateInputOutputNames" def{
-                hdlTargets=[VHDL]
-              , expectClashFail=Just (def, "Tried create a signal called 'a', but identifier generation returned")
-              }
-            , runTest "OutputBusWidthExceeded" def{
-                hdlTargets=[VHDL, Verilog, SystemVerilog]
-              , expectClashFail=Just (def, "Probe signals must be been between 1 and 256 bits wide.")
-              }
-            , runTest "OutputProbesExceeded" def{
-                hdlTargets=[VHDL, Verilog, SystemVerilog]
-              , expectClashFail=Just (def, "At most 256 input/output probes are supported.")
-              }
-            , runTest "InputBusWidthExceeded" def{
-                hdlTargets=[VHDL, Verilog, SystemVerilog]
-              , expectClashFail=Just (def, "Probe signals must be been between 1 and 256 bits wide.")
-              }
-            , runTest "InputProbesExceeded" def{
-                hdlTargets=[VHDL, Verilog, SystemVerilog]
-              , expectClashFail=Just (def, "At most 256 input/output probes are supported.")
-              }
-            ]
-          ]
-        ]
       , clashTestGroup "InvalidPrimitive"
         [ runTest "InvalidPrimitive" def{
             hdlTargets=[VHDL]
@@ -482,154 +448,6 @@ runClashTest = defaultMain $ clashTestRoot
       , clashTestGroup "BoxedFunctions"
         [ runTest "DeadRecursiveBoxed" def{hdlSim=[]}
         ]
-      , clashTestGroup "Cores"
-        [ clashTestGroup "Xilinx"
-          [ runTest "TdpBlockRam" def
-            { -- Compiling with VHDL gives:
-              --   https://github.com/clash-lang/clash-compiler/issues/2446
-              hdlTargets = [Verilog]
-            , hdlLoad = [Vivado]
-            , hdlSim = [Vivado]
-            , clashFlags=["-fclash-hdlsyn", "Vivado"]
-            , buildTargets=BuildSpecific [ "normalWritesTB", "writeEnableWritesTB" ]
-            }
-          , let _opts = def{ hdlTargets=[VHDL, Verilog]
-                           , hdlLoad=[Vivado]
-                           , hdlSim=[Vivado]
-                             -- addShortPLTB now segfaults :-(
-                           , buildTargets=BuildSpecific [ "addBasicTB"
-                                                        , "addEnableTB"
-                                                        -- , "addShortPLTB"
-                                                        , "subBasicTB"
-                                                        , "mulBasicTB"
-                                                        , "divBasicTB"
-                                                        , "compareBasicTB"
-                                                        , "compareEnableTB"
-                                                        , "fromUBasicTB"
-                                                        , "fromUEnableTB"
-                                                        , "fromSBasicTB"
-                                                        , "fromSEnableTB"
-                                                        ]
-                           }
-            in runTest "Floating" _opts
-          , runTest "XpmCdcArraySingle" $ def
-              { hdlTargets=[VHDL, Verilog]
-              , hdlLoad=[Vivado]
-              , hdlSim=[Vivado]
-              , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
-              }
-          , runTest "XpmCdcGray" $ def
-              { hdlTargets=[VHDL, Verilog]
-              , hdlLoad=[Vivado]
-              , hdlSim=[Vivado]
-              , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
-              }
-          , runTest "XpmCdcHandshake" $ def
-              { hdlTargets=[VHDL, Verilog]
-              , hdlLoad=[Vivado]
-              , hdlSim=[Vivado]
-              , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..6]]
-              }
-          , runTest "XpmCdcPulse" $ def
-              { hdlTargets=[VHDL, Verilog]
-              , hdlLoad=[Vivado]
-              , hdlSim=[Vivado]
-              , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
-              }
-          , runTest "XpmCdcSingle" $ def
-              { hdlTargets=[VHDL, Verilog]
-              , hdlLoad=[Vivado]
-              , hdlSim=[Vivado]
-              , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
-              }
-          , runTest "XpmCdcSyncRst" $ def
-              { hdlTargets=[VHDL, Verilog]
-              , hdlLoad=[Vivado]
-              , hdlSim=[Vivado]
-              , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
-              }
-          , runTest "DnaPortE2" def
-              { hdlTargets=[VHDL, Verilog]
-              , hdlLoad=[Vivado]
-              , hdlSim=[Vivado]
-              }
-          , clashTestGroup "DcFifo"
-            [ let _opts =
-                    def{ hdlTargets=[VHDL, Verilog]
-                       , hdlLoad=[Vivado]
-                       , hdlSim=[Vivado]
-                       }
-              in runTest "Basic" _opts
-            , let _opts = def{ hdlTargets=[VHDL, Verilog]
-                             , hdlLoad=[Vivado]
-                             , hdlSim=[Vivado]
-                             , buildTargets=BuildSpecific [ "testBench_17_2"
-                                                          , "testBench_2_17"
-                                                          , "testBench_2_2"
-                                                          ]
-                             }
-              in runTest "Lfsr" _opts
-            ]
-          , let _opts =
-                  def{ hdlTargets=[VHDL, Verilog, SystemVerilog]
-                     , hdlLoad=[Vivado]
-                     , hdlSim=[Vivado]
-                     , buildTargets=BuildSpecific [ "noInputTrue"
-                                                  , "noInputFalse"
-                                                  , "noInputLow"
-                                                  , "noInputHigh"
-                                                  , "noInputSigned"
-                                                  , "noInputUnsigned"
-                                                  , "noInputBitVector"
-                                                  , "noInputPair"
-                                                  , "noInputVec"
-                                                  , "noInputCustom"
-                                                  , "noInputNested"
-                                                  , "singleInputBool"
-                                                  , "singleInputBit"
-                                                  , "singleInputSigned"
-                                                  , "singleInputUnsigned"
-                                                  , "singleInputBitVector"
-                                                  , "singleInputPair"
-                                                  , "singleInputVec"
-                                                  , "singleInputCustom"
-                                                  , "singleInputNested"
-                                                  , "multipleInputs"
-                                                  , "inputsAndOutputs"
-                                                  , "withSetName"
-                                                  , "withSetNameNoResult"
-                                                  ]
-                     }
-            in runTest "VIO" _opts
-          , let _opts =
-                  def{ hdlTargets=[VHDL, Verilog, SystemVerilog]
-                     , hdlLoad=[Vivado]
-                     , hdlSim=[Vivado]
-                     , buildTargets=BuildSpecific [ "testWithDefaultsOne"
-                                                  , "testWithDefaultsThree"
-                                                  , "testWithLefts"
-                                                  , "testWithRights"
-                                                  , "testWithRightsSameCu"
-                                                  ]
-                     }
-            in runTest "Ila" _opts
-          , let _opts =
-                  def{ hdlTargets=[VHDL, Verilog, SystemVerilog]
-                     , buildTargets=BuildSpecific [ "testWithDefaultsOne"
-                                                  , "testWithDefaultsThree"
-                                                  , "testWithLefts"
-                                                  , "testWithRights"
-                                                  , "testWithRightsSameCu"
-                                                  ]
-                     }
-            in outputTest "Ila" _opts
-          , outputTest "VIO" def{
-              hdlTargets=[VHDL]
-            , buildTargets=BuildSpecific ["withSetName", "withSetNameNoResult"]
-            }
-          , runTest "T2549" def{hdlTargets=[Verilog],hdlSim=[]}
-          ]
-        ]
       , clashTestGroup "CSignal"
         [ runTest "MAC" def{hdlSim=[]}
         , runTest "CBlockRamTest" def{hdlSim=[]}

diff --git a/tests/clash-testsuite.cabal b/tests/clash-testsuite.cabal
@@ -64,7 +64,6 @@ common basic-config
     -- testsuite to compile, but we do when running it.
     -- Leaving it out will cause the testsuite to compile
     -- it anyway so we're better off doing it beforehand.
-    clash-cores,
     clash-ghc,
     clash-lib,
     clash-prelude

diff --git a/tests/shouldfail/Cores/Xilinx/VIO/DuplicateInputNames.hs b/tests/shouldfail/Cores/Xilinx/VIO/DuplicateInputNames.hs
diff --git a/tests/shouldfail/Cores/Xilinx/VIO/DuplicateInputOutputNames.hs b/tests/shouldfail/Cores/Xilinx/VIO/DuplicateInputOutputNames.hs
diff --git a/tests/shouldfail/Cores/Xilinx/VIO/DuplicateOutputNames.hs b/tests/shouldfail/Cores/Xilinx/VIO/DuplicateOutputNames.hs
diff --git a/tests/shouldfail/Cores/Xilinx/VIO/InputBusWidthExceeded.hs b/tests/shouldfail/Cores/Xilinx/VIO/InputBusWidthExceeded.hs
diff --git a/tests/shouldfail/Cores/Xilinx/VIO/InputProbesExceeded.hs b/tests/shouldfail/Cores/Xilinx/VIO/InputProbesExceeded.hs
diff --git a/tests/shouldfail/Cores/Xilinx/VIO/OutputBusWidthExceeded.hs b/tests/shouldfail/Cores/Xilinx/VIO/OutputBusWidthExceeded.hs
diff --git a/tests/shouldfail/Cores/Xilinx/VIO/OutputProbesExceeded.hs b/tests/shouldfail/Cores/Xilinx/VIO/OutputProbesExceeded.hs