Explicitly export functions

clash-cores/src/Clash/Cores/Sgmii.hs

@@ -55,7 +55,12 @@
 --   basis and they are always transmitted to @TXD@, this port should only be
 --   read when @RX_DV@ is asserted as invalid data might be provided when it is
 --   not.
-module Clash.Cores.Sgmii where
+module Clash.Cores.Sgmii (
+  sgmii,
+  sgmiiRA,
+  sgmiiRx,
+  sgmiiTx,
+) where
 
 import Clash.Cores.LineCoding8b10b
 import Clash.Cores.Sgmii.AutoNeg

clash-cores/src/Clash/Cores/Sgmii/AutoNeg.hs

@@ -8,7 +8,13 @@
 --   Maintainer  :  QBayLogic B.V. <devops@qbaylogic.com>
 --
 --   Auto-negotiation process, as defined in IEEE 802.3 Figure 37-6
-module Clash.Cores.Sgmii.AutoNeg where
+module Clash.Cores.Sgmii.AutoNeg (
+  AutoNegState (..),
+  Timeout,
+  autoNeg,
+  autoNegO,
+  autoNegT,
+) where
 
 import Clash.Cores.Sgmii.Common
 import Clash.Prelude

clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs

@@ -9,7 +9,12 @@
 --
 --   Bit slip function that word-aligns a stream of bits based on received
 --   comma values
-module Clash.Cores.Sgmii.BitSlip where
+module Clash.Cores.Sgmii.BitSlip (
+  BitSlipState (..),
+  bitSlip,
+  bitSlipO,
+  bitSlipT,
+) where
 
 import Clash.Cores.Sgmii.Common
 import Clash.Prelude
@@ -28,10 +33,6 @@ data BitSlipState
   | BSOk {_s :: BitVector 20, _n :: Index 10}
   deriving (Generic, NFDataX, Eq, Show)
 
--- | Reverse the bits of a 'BitVector'
-reverseBV :: (KnownNat n) => BitVector n -> BitVector n
-reverseBV = v2bv . reverse . bv2v
-
 -- | State transition function for 'bitSlip', where the initial state is the
 --   training state, and after 8 consecutive commas have been detected at the
 --   same index in the status register it moves into the 'BSOk' state where the

clash-cores/src/Clash/Cores/Sgmii/Common.hs

@@ -95,6 +95,10 @@ orNothing :: Bool -> a -> Maybe a
 orNothing True a = Just a
 orNothing False _ = Nothing
 
+-- | Reverse the bits of a 'BitVector'
+reverseBV :: (KnownNat n) => BitVector n -> BitVector n
+reverseBV = v2bv . reverse . bv2v
+
 -- | Code group that corresponds to K28.5 with negative disparity
 cgK28_5N :: Cg
 cgK28_5N = 0b0101111100

clash-cores/src/Clash/Cores/Sgmii/PcsReceive.hs

@@ -8,7 +8,12 @@
 --   Maintainer  :  QBayLogic B.V. <devops@qbaylogic.com>
 --
 --   PCS receive process, as defined in IEEE 802.3 Figure 36-7a and 36-7b
-module Clash.Cores.Sgmii.PcsReceive where
+module Clash.Cores.Sgmii.PcsReceive (
+  PcsReceiveState (..),
+  pcsReceive,
+  pcsReceiveO,
+  pcsReceiveT,
+) where
 
 import Clash.Cores.LineCoding8b10b
 import Clash.Cores.Sgmii.Common

clash-cores/src/Clash/Cores/Sgmii/PcsTransmit.hs

@@ -7,7 +7,7 @@
 --
 --   Top level module for the PCS transmit block, that combines the processes
 --   that are defined in the two submodules @CodeGroup@ and @OrderedSet@.
-module Clash.Cores.Sgmii.PcsTransmit where
+module Clash.Cores.Sgmii.PcsTransmit (pcsTransmit) where
 
 import Clash.Cores.Sgmii.Common
 import Clash.Cores.Sgmii.PcsTransmit.CodeGroup

clash-cores/src/Clash/Cores/Sgmii/PcsTransmit/CodeGroup.hs

@@ -9,7 +9,11 @@
 --
 --   Code group process of the PCS transmit block, as defined in IEEE 802.3
 --   Figure 36-6
-module Clash.Cores.Sgmii.PcsTransmit.CodeGroup where
+module Clash.Cores.Sgmii.PcsTransmit.CodeGroup (
+  CodeGroupState (..),
+  codeGroupO,
+  codeGroupT,
+) where
 
 import Clash.Cores.LineCoding8b10b
 import Clash.Cores.Sgmii.Common

clash-cores/src/Clash/Cores/Sgmii/PcsTransmit/OrderedSet.hs

@@ -8,7 +8,10 @@
 --
 --   Ordered set process of the PCS transmit block, as defined in IEEE 802.3
 --   Figure 36-5
-module Clash.Cores.Sgmii.PcsTransmit.OrderedSet where
+module Clash.Cores.Sgmii.PcsTransmit.OrderedSet (
+  OrderedSetState (..),
+  orderedSetT,
+) where
 
 import Clash.Cores.Sgmii.Common
 import Clash.Prelude

clash-cores/src/Clash/Cores/Sgmii/RateAdapt.hs

@@ -7,7 +7,10 @@
 --
 --   Functions for the rate adaptation blocks that are required for lower bit
 --   rates than 1000 Mbps
-module Clash.Cores.Sgmii.RateAdapt where
+module Clash.Cores.Sgmii.RateAdapt (
+  rateAdaptRx,
+  rateAdaptTx,
+) where
 
 import Clash.Cores.Sgmii.Common
 import Clash.Prelude

clash-cores/src/Clash/Cores/Sgmii/Sync.hs

@@ -9,7 +9,14 @@
 --   Maintainer  :  QBayLogic B.V. <devops@qbaylogic.com>
 --
 --   Synchronization process, as defined in IEEE 802.3 Figure 36-9
-module Clash.Cores.Sgmii.Sync where
+module Clash.Cores.Sgmii.Sync (
+  SyncState (..),
+  outputQueueO,
+  outputQueueT,
+  sync,
+  syncO,
+  syncT,
+) where
 
 import Clash.Cores.LineCoding8b10b
 import Clash.Cores.Sgmii.Common