VIO probes always output undefined, making them hard to use in simulation

[martijnbastiaan]

I don't have a suggestion on how to handle this, unfortunately. Perhaps it is as simple as pointing out the existence of:

clash-compiler/clash-prelude/src/Clash/Magic.hs

Lines 242 to 245 in b80511b

	-- | 'True' in Haskell/Clash simulation. Replaced by 'False' when generating HDL.
	clashSimulation :: Bool
	clashSimulation = True
	{-# NOINLINE clashSimulation #-}

[christiaanb]

I wonder which use case is the most common:

1. Arguments are only provided by VIO; results are only consumed by VIO
2. VIO used for debugging values passed to a subcircuit

I assume situation 2 is the most common, in which case it might be worth to make a version that muxes between the original argument and the VIO probe. It would pick the original argument in simulation only, and would pick the VIO probe when synthesized. We should then make this the default behavior and use the most convenient name; and maker the VIO probe that outputs undefined the special case with a less convenient name.

[leonschoorl]

You have to provide an initial value for each probe.
Why don't we just always output those values in simulation?

[leonschoorl]

The hardware-in-the-loop tests on bitide use option 1., where a script on a computer uses a VIO to start a test in the FPGA and to read the result of the test back.